# Mobile processor

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Processor found in mobile devices

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An [Intel Pentium](/source/Pentium_(original)) Mobile, clocked at 300 MHz (1998)

A **mobile processor** is a [microprocessor](/source/Microprocessor) designed for [mobile devices](/source/Mobile_computer) such as [laptops](/source/Laptop) and [cell phones](/source/Cell_phone).

A CPU chip is designed for portable computers to run [fanless](/source/Fanless_computer), under 10 to 15W, which is cool enough without a fan.[1] It is typically housed in a smaller chip package, but more importantly, in order to run cooler, it uses lower voltages than its [desktop](/source/Desktop_computer) counterpart and has more [sleep mode](/source/Sleep_mode) capability. A mobile processor can be throttled down to different power levels or sections of the chip can be turned off entirely when not in use. Further, the [clock frequency](/source/Clock_frequency) may be stepped down under low processor loads. This stepping down conserves power and prolongs [battery life](/source/Rechargeable_battery).

## In laptops

One of the main characteristics differentiating [laptop](/source/Laptop) processors from other CPUs is [low power consumption](/source/Low-power_electronics), which is not without tradeoffs: they also tend to not perform as well as their desktop counterparts.[2]

The notebook processor has become an important [market segment](/source/Market_segment) in the [semiconductor industry](/source/Semiconductor_industry). Notebook computers are a popular format of the broader category of [mobile computers](/source/Mobile_computing). The objective of a notebook computer is to provide the performance and functionality of a [desktop computer](/source/Desktop_computer) in a [portable](/source/Portable_computer) size and weight.

Cell phones and PDAs use "[system on a chip](/source/System_on_a_chip)" integrated circuits that use less power than most notebook processors.

While it is possible to use desktop processors in laptops, this practice is generally not recommended, as desktop processors heat faster than notebook processors and drain batteries faster.

## Examples

### Current

- [ARM architecture](/source/ARM_architecture) (used in [Chromebooks](/source/Chromebook), [Windows 10](/source/Windows_10), [Windows 11](/source/Windows_11) laptops, Linux [netbooks](/source/Netbook) and recent [Macs](/source/Mac_transition_to_Apple_silicon)) - [Apple M series](/source/Apple_M_series) - [Huawei](/source/Huawei): [HiSilicon Kirin](/source/HiSilicon) - [MediaTek](/source/MediaTek) - [Nvidia](/source/Nvidia): [Tegra](/source/Tegra) - [Qualcomm](/source/Qualcomm): [Snapdragon](/source/Qualcomm_Snapdragon) - [Rockchip](/source/Rockchip) - [Samsung Electronics](/source/Samsung_Electronics): [Exynos](/source/Exynos)

- [x86](/source/X86) - [AMD](/source/AMD): [Ryzen](/source/Ryzen), [Athlon](/source/Athlon), and [A-Series APU](/source/AMD_Accelerated_Processing_Unit) - [Intel](/source/Intel): [Xeon](/source/Xeon) mobile, [Core](/source/Intel_Core), [Pentium](/source/Pentium), and [Celeron](/source/Celeron)

### Former

- [PowerPC](/source/PowerPC) - [Motorola](/source/Motorola) and [Freescale Semiconductor](/source/Freescale_Semiconductor) made [PowerPC G4](/source/PowerPC_G4) processors for the pre-Intel [Apple Computer](/source/Apple_Computer) notebooks.

- [x86](/source/X86) - [Transmeta](/source/Transmeta): [Crusoe](/source/Transmeta_Crusoe) and [Efficeon](/source/Transmeta_Efficeon) - [Intel](/source/Intel): [Pentium M](/source/Pentium_M) - [AMD](/source/AMD): [Mobile Athlon II](/source/Athlon_II), [Mobile Athlon 64](/source/Mobile_Athlon_64), [Mobile Sempron](/source/Mobile_Sempron)

## References

1. **[^](#cite_ref-1)** ["Fanless computer boards are pushing 15W to the limit"](https://www.electronicsweekly.com/news/fanless-computer-boards-are-pushing-15w-to-the-limit-2015-10/). 15 October 2015.

1. **[^](#cite_ref-2)** ["Intel Processor Letter Meanings \[2022 Guide\]"](https://www.gamingscan.com/intel-processor-letter-meanings/). 10 January 2022.

v t e Processor technologies Models Abstract machine Stored-program computer Finite-state machine with datapath Hierarchical Deterministic finite automaton Queue automaton Cellular automaton Quantum cellular automaton Turing machine Alternating Turing machine Universal Post–Turing Quantum Nondeterministic Turing machine Probabilistic Turing machine Hypercomputation Zeno machine Belt machine Stack machine Register machines Counter Pointer Random-access Random-access stored program Architecture Microarchitecture Von Neumann Harvard modified Dataflow Transport-triggered Cellular Endianness Memory access NUMA HUMA Load–store Register/memory Cache hierarchy Memory hierarchy Virtual memory Secondary storage Heterogeneous Fabric Multiprocessing Cognitive Neuromorphic Instruction set architectures Types Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes Instruction sets Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others Execution Instruction pipelining Pipeline stall Operand forwarding Classic RISC pipeline Hazards Data dependency Structural Control False sharing Out-of-order Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue Speculative Branch prediction Memory dependence prediction Parallelism Level Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed Multithreading Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD Processor performance Transistor count Instructions per cycle (IPC) Cycles per instruction (CPI) Instructions per second (IPS) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic updates per second (SUPS) Performance per watt (PPW) Cache performance metrics Computer performance by orders of magnitude Types Central processing unit (CPU) Graphics processing unit (GPU) GPGPU Vector Barrel Stream Tile processor Coprocessor PAL ASIC FPGA FPOA CPLD Multi-chip module (MCM) System in a package (SiP) Package on a package (PoP) By application Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor Systems on chip System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC) Hardware accelerators Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor Word size 1-bit 4-bit 8-bit 12-bit 15-bit 16-bit 24-bit 32-bit 48-bit 64-bit 128-bit 256-bit 512-bit bit slicing others variable Core count Single-core Multi-core Manycore Heterogeneous architecture Components Core Cache CPU cache Scratchpad memory Data cache Instruction cache replacement policies coherence Bus Clock rate Clock signal FIFO Functional units Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder Logic Combinational Sequential Glue Logic gate Quantum Array Registers Processor register Status register Stack register Register file Memory buffer Memory address register Program counter Control unit Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter Datapath Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter Circuitry Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch Power management PMU APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Performance per watt (PPW) Related History of general-purpose CPUs Microprocessor chronology Processor design Digital electronics Hardware security module Semiconductor device fabrication Tick–tock model Pin grid array Chip carrier

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Adapted from the Wikipedia article [Mobile processor](https://en.wikipedia.org/wiki/Mobile_processor) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Mobile_processor?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.