# Memory semantics (computing)

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Process logic used to control access to shared memory locations

In [computing](/source/Computing) and [parallel processing](/source/Parallel_computing), **memory semantics** refers to the process logic used to control access to [shared memory](/source/Shared_memory_architecture) locations, or at a higher level to shared variables in the presence of multiple threads or processors.[1]

Memory semantics may also be defined for [transactional memory](/source/Transactional_memory), where issues related to the interaction of transactions and [locks](/source/Lock_(computer_science)), and user-level actions need to be defined and specified.[2]

## See also

- [Consistency model](/source/Consistency_model)

## References

1. **[^](#cite_ref-1)** *Advances in Computers, Volume 79* by [Marvin V. Zelkowitz](/source/Marvin_Victor_Zelkowitz) 2010 [ISBN](/source/ISBN_(identifier)) [0123810272](https://en.wikipedia.org/wiki/Special:BookSources/0123810272) pages 104-105

1. **[^](#cite_ref-2)** *Towards transactional memory semantics for C++* by Tatiana Shpeisman et al in *Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures* 2009 [ISBN](/source/ISBN_(identifier)) [978-1-60558-606-9](https://en.wikipedia.org/wiki/Special:BookSources/978-1-60558-606-9) [\[1\]](http://dl.acm.org/citation.cfm?id=1584012)

v t e Parallel computing General Distributed computing Parallel computing Parallel algorithm Massively parallel Cloud computing High-performance computing Multiprocessing Manycore processor GPGPU Computer network Systolic array Levels Bit Instruction Thread Task Data Memory Loop Pipeline Multithreading Temporal Simultaneous (SMT) Simultaneous and heterogenous Speculative (SpMT) Preemptive Cooperative Clustered multi-thread (CMT) Hardware scout Theory PRAM model PEM model Analysis of parallel algorithms Amdahl's law Gustafson's law Cost efficiency Karp–Flatt metric Slowdown Speedup Elements Process Thread Fiber Instruction window Array Coordination Multiprocessing Memory coherence Cache coherence Cache invalidation Barrier Synchronization Application checkpointing Programming Stream processing Dataflow programming Models Implicit parallelism Explicit parallelism Concurrency Non-blocking algorithm Hardware Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing MISD MIMD Dataflow architecture Pipelined processor Superscalar processor Vector processor Multiprocessor symmetric asymmetric Memory shared distributed distributed shared UMA NUMA COMA Massively parallel computer Computer cluster Beowulf cluster Grid computer Hardware acceleration APIs Ateji PX Boost Chapel HPX Charm++ Cilk Coarray Fortran CUDA Dryad C++ AMP Global Arrays GPUOpen MPI OpenMP OpenCL OpenHMPP OpenACC Parallel Extensions PVM pthreads RaftLib ROCm UPC TBB ZPL Problems Automatic parallelization Cache stampede Deadlock Deterministic algorithm Embarrassingly parallel Parallel slowdown Race condition Software lockout Scalability Starvation Category: Parallel computing

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Adapted from the Wikipedia article [Memory semantics (computing)](https://en.wikipedia.org/wiki/Memory_semantics_(computing)) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Memory_semantics_(computing)?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.