# Machine Check Architecture
> Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Machine_Check_Architecture
> Markdown URL: https://mediated.wiki/source/Machine_Check_Architecture.md
> Source: https://en.wikipedia.org/wiki/Machine_Check_Architecture
> Source revision: 1312303706
> License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/)
{{Multiple issues|
{{More citations needed|date=December 2007}}
{{Update|date=February 2014}}
}}
In [computing](/source/computing), '''Machine Check Architecture''' ('''MCA''') is an [Intel](/source/Intel) and [AMD](/source/AMD) mechanism in which the [CPU](/source/CPU) reports hardware errors to the [operating system](/source/operating_system).
Intel's P6 and Pentium 4 family processors, AMD's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, [ECC](/source/Error_detection_and_correction) errors, parity errors, [cache](/source/CPU_cache) errors, and [translation lookaside buffer](/source/translation_lookaside_buffer) errors.[{{cite book |date=September 2023 |url=https://www.intel.com/content/www/us/en/content-details/789580/intel-64-and-ia-32-architectures-software-developer-s-manual-volume-3b-system-programming-guide-part-2.html |title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2 |publisher=[Intel](/source/Intel) Corporation |page=16{{hyphen}}1 |access-date=September 19, 2025 }}] It consists of a set of model-specific registers ([MSR](/source/Model-specific_register)s) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.