# I.MX > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/I.MX > Markdown URL: https://mediated.wiki/source/I.MX.md > Source: https://en.wikipedia.org/wiki/I.MX > Source revision: 1345380628 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) {{Short description|Family of microcontrollers}} {{lowercase title}} The '''i.MX''' series is a family of [ARM architecture-based](/source/ARM_architecture_family) [system-on-chip (SoC)](/source/Microprocessor) processors designed by [NXP Semiconductors](/source/NXP_Semiconductors) for multimedia and [embedded applications](/source/Embedded_Application_Programming_Interface) focused on low-power consumption.{{cite web |last1=Turley |first1=Jim |date=1 November 2017 |title=NXP's New i.MX RT1050 Gets Edgy |url=https://www.eejournal.com/article/nxps-new-i-mx-rt1050-gets-edgy/ |access-date=17 August 2020 |website=eejournal.com |publisher=Electronics Engineering Journal}} Originally developed by [Freescale Semiconductor](/source/Freescale_Semiconductor) (acquired by NXP in 2015),{{Cite web |date=2015-12-07 |title=NXP closes deal to buy Freescale and create top auto chipmaker |url=https://www.cnbc.com/2015/12/07/nxp-closes-deal-to-buy-freescale-and-create-top-auto-chipmaker.html |access-date=2025-11-15 |website=CNBC |language=en}} the i.MX application processors integrate multiple processing units including [CPU core](/source/CPU_core)s, [graphics processing unit](/source/graphics_processing_unit)s (GPUs), and [video processing units](/source/Video_Processing_Unit) (VPUs) onto a single [die](/source/Die_(integrated_circuit)). The i.MX family is qualified for automotive, industrial, and consumer markets with most products guaranteed for a production lifetime of 10 to 15 years.{{cite web|url=http://www.freescale.com/productlongevity |title=Product Longevity|NXP |website=Freescale.com |access-date=2016-09-24}} i.MX originally stood for "innovative Multimedia eXtension" and was previously known as the "DragonBall MX" family, the fifth generation of [Freescale DragonBall](/source/Freescale_DragonBall) microcontrollers. Notable devices that use i.MX processors include [Ford Sync](/source/Ford_Sync) automotive systems,{{Cite web |title=NXP and Ford Collaborate to Deliver Next-Generation Connected Car Experiences and Expanded Services |url=https://www.nxp.com/pages/:NW-NXP-AND-FORD-COLLABORATE-TO-DELIVER-NEXT-GEN |access-date=2025-08-19 |website=www.nxp.com}} the [Amazon Kindle](/source/Amazon_Kindle),{{Cite web |last=Parish |first=Joseph |date=2012-01-09 |title=Freescale is making new 'lite' processors for e-readers and entry-level tablets |url=https://www.theverge.com/2012/1/9/2692247/freescale-is-making-new-lite-processors-for-e-readers-and-entry-level |access-date=2025-08-19 |website=The Verge |language=en-US}} [Zune](/source/Zune) (except for Zune HD), [Purism](/source/Purism_(company))'s [Librem 5](/source/Librem_5), and various embedded systems and [single-board computer](/source/single-board_computer)s. == History == The i.MX family was launched in 2001/2002 with the original [DragonBall MX1](/source/Freescale_DragonBall) series based on ARM920T architecture.{{Cite web |title=Best-in-class claim for new DragonBalls: News from Freescale Semiconductor |url=https://old.electronicstalk.com/news/mot/mot106.html |access-date=2025-11-15 |website=old.electronicstalk.com}} Freescale Semiconductor developed successive generations through the 2000s and 2010s, progressively adopting newer ARM architectures from ARM9 through ARM11 to [ARM Cortex](/source/ARM_Cortex) designs. In 2007, Freescale licensed AMD's [Imageon](/source/Imageon) graphics technology to integrate GPU capabilities into later i.MX5 series processors. NXP acquired Freescale in 2015 in a deal worth nearly $12 billion, with the i.MX product line continuing development under NXP. The i.MX family has expanded significantly over time with newer generations incorporating more advanced ARM cores, improved manufacturing processes,{{Cite web |title=NXP's i.MX 94 Family: Redefining Industrial and Automotive Processing |url=https://www.microchipusa.com/articles/nxp/nxps-i-mx-94-family-redefining-industrial-and-automotive-processing |access-date=2025-11-15 |website=Microchip USA - TRANSPARENCY INNOVATION EFFICIENCY |language=en}} and specialized variants for [IoT](/source/IoT), automotive, and industrial applications. The i.MX RT crossover [microcontroller](/source/microcontroller) series was introduced in 2017, combining microcontroller-like features with applications processor performance. == {{anchor|i.MX1}}i.MX 1 series == thumb|Freescale DragonBall MX-1 Microprocessor (BGA Package). The series was later renamed to i.MX. Launched in 2001/2002, the i.MX / MX-1 series is based on the ARM920T architecture. * i.MX1 = 200 MHz ARM920T * i.MXS = 100 MHz ARM920T * i.MXL = 150-200 MHz ARM920T ==i.MX 2 series== The i.MX2x series is a family of processors based on the [ARM9](/source/ARM_architecture) architecture (ARM926EJ-S), designed in a 90 nm process. ===i.MX 21 family=== The i.MX21 family is designed for low power handheld devices. It was launched in 2003. * i.MX21 = 266 MHz ARM9 platform + CIF VPU (decode/encode) + security * i.MX21S = 266 MHz ARM9 platform + security ===i.MX 27 family=== The i.MX27 family is designed for videotelephony and video surveillance. It was launched in 2007. * i.MX27 = 400 MHz ARM9 platform + D1 VPU (decode/encode) + [IPU](/source/Digital_image_processing) + security * i.MX27L = 400 MHz ARM9 platform + IPU + security ===i.MX 25 family=== The i.MX25 family was launched in 2009. It especially integrates key security features in hardware. The high-end member of the family, i.MX258, integrates a 400 MHz ARM9 CPU platform + LCDC (LCD controller) + security block and supports mDDR-SDRAM at 133 MHz. * i.MX258 (industrial) = 400 MHz ARM9 platform + LCDC (with touch screen support) + security * i.MX257 (consumer/industrial) = 400 MHz ARM9 platform + LCDC (with touch screen support) * i.MX253 (consumer/industrial) = 400 MHz ARM9 platform + LCDC + security (no touch) * i.MX255 (automotive) = 400 MHz ARM9 platform + LCDC (with touch screen support) + security * i.MX251 (automotive) = 400 MHz ARM9 platform + security ==={{anchor|iMX233}}i.MX 23 family=== The i.MX233 processor (formerly known as SigmaTel STMP3780 of the [STMP37xx](/source/STMP37xx) family), launched in 2009, integrates a [Power Management Unit](/source/Power_Management_Unit) (PMU) and a stereo audio codec within the silicon, thus removing the need for external power management chip and audio codec chip. * i.MX233 (consumer) = 454 MHz ARM9 platform + LCD Controller (with touch screen support) + Pixel Pipeline + security + Power Management Unit + audio codec. Provided in 128LQFP or 169 BGA packages. ===i.MX 28 family=== The i.MX28 family was launched in 2010. It integrates key security features in hardware, an ADC, and the power management unit. It supports mDDR, LV-DDR2, and DDR2-SDRAM memory at 200 MHz. * i.MX287 (industrial) = 454 MHz ARM9 platform + LCDC (with touch screen support) + security + power management + dual CAN interface + dual Ethernet + L2 Switch * i.MX286 (industrial) = 454 MHz ARM9 platform + LCDC (with touch screen support) + security + power management + dual CAN interface + single Ethernet * i.MX285 (automotive) = 454 MHz ARM9 platform + LCDC (with touch screen support) + security + power management + dual CAN interface * i.MX283 (consumer/industrial) = 454 MHz ARM9 platform + LCDC (with touch screen support) + security + power management + single Ethernet * i.MX281 (automotive) = 454 MHz ARM9 platform + security + power management + dual CAN interface + single Ethernet * i.MX280 (consumer/industrial) = 454 MHz ARM9 platform + security + power management + single Ethernet ==i.MX 3 series== The i.MX3x series is a family of processors based on the [ARM11](/source/ARM_architecture) architecture (ARM1136J(F)-S mainly), designed in a 90 nm process. ===i.MX 31 family=== The i.MX31 was launched in 2005. It integrates a 532 MHz ARM1136JF-S CPU platform (with vector floating point unit, L1 caches and 128KB L2 caches) + Video Processing Unit (VPU) + 3D [GPU](/source/GPU) ([OpenGL](/source/OpenGL) ES 1.1) + [IPU](/source/Digital_image_processing) + security block. It supports mDDR-SDRAM at 133 MHz. The 3D and VPU acceleration is provided by the [PowerVR MBX Lite](/source/PowerVR). * i.MX31 (consumer/industrial/automotive) = 532 MHz ARM1136 platform + VPU + 3D GPU + IPU + security * i.MX31L (consumer/industrial/automotive) = 532 MHz ARM1136 platform + VPU + IPU + security ===i.MX 37 family=== The i.MX37 processor is designed for portable media players. It was launched in 2008. * i.MX 37 (consumer) = 532 MHz ARM1176 CPU platform + D1 VPU (multiformat D1 decode) + IPU + security block It supports mDDR-SDRAM at 133 MHz. ===i.MX 35 family=== thumb|Freescale Semiconductor MCIMX353DJQ5C The i.MX35 family was launched in 2009 and is the replacement for the i.MX31 series. The high-end member of the family, i.MX357, integrates a 532 MHz ARM1136J(F)-S CPU platform (with Vector Floating Point unit, L1 caches and 128KB L2 cache), a 2.5D [GPU](/source/GPU) ([OpenVG](/source/OpenVG) 1.1), a [IPU](/source/Digital_image_processing), and a security block. It supports DDR2-SDRAM at 133 MHz. * i.MX357 (consumer/industrial) = 532 MHz ARM1136J(F)-S CPU platform + 2.5D GPU + IPU + security * i.MX353 (consumer/industrial) = 532 MHz ARM1136J(F)-S CPU platform + IPU + security * i.MX356 (automotive) = 532 MHz ARM1136J(F)-S CPU platform + 2.5D GPU + IPU + security * i.MX355 (automotive) = 532 MHz ARM1136J(F)-S CPU platform + IPU + security * i.MX351 (automotive) = i.MX355 with no LCD interface ==i.MX 5 series== The i.MX5x series is based on the [ARM Cortex A8](/source/ARM_Cortex_A8) core. It consists of two families: the i.MX51 family (high-end multimedia devices like [smartbook](/source/smartbook) or automotive infotainment) and the i.MX50 family ([eReaders](/source/eReaders)). It is designed in a 65 nm process. Freescale licensed ATI's Imageon technology in 2007,{{cite web |title=Freescale Licenses AMD Graphics Technology to Deliver Exceptional Mobile Visuals |url=http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543_15008~120703,00.html |archive-url=https://web.archive.org/web/20071217050403/http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543_15008~120703,00.html |url-status=dead |archive-date=17 December 2007 |access-date=14 September 2019 |date=17 December 2007}} and some i.MX5 models include an [Imageon](/source/Imageon) Z460 [GPU](/source/graphics_processing_unit). ===i.MX 51 family=== The high-end member of the family, i.MX515, integrates an 800 MHz [ARM Cortex A8](/source/ARM_Cortex_A8) CPU platform (with [NEON](/source/ARM_NEON) co-processor, Vector [Floating Point](/source/Floating-point_arithmetic) Unit, L1 caches and 256KB L2 cache) + multi-format HD 720p decode / D1 encode hardware video codecs (VPU, Video Processing Unit) + [Imageon](/source/Imageon) Z430 3D [GPU](/source/graphics_processing_unit) (OpenGL ES 2.0) + 2.5D GPU (OpenVG 1.1) + [IPU](/source/Digital_image_processing) + security block.{{cite web |last1=Vahe |first1=Gerald |last2=Chang |first2=Marsha |title=Using Freescale Linux® Package to Take Full Advantage of the Rich Hardware Acceleration Blocks of the i.MX51 (Part 1) |url=https://usermanual.wiki/m/43671a3bf1be5b914797118110c01142f3bd7f36cdd108c778dbcfd01c0c822d.pdf |access-date=1 May 2023 |publisher=Freescale/NXP}}{{cite web |title=MCIMX51 Multimedia Applications Processor Reference Manual |url=https://www.nxp.com/files-static/dsp/doc/ref_manual/MCIMX51RM.pdf |publisher=Freescale Semiconductor |access-date=1 May 2023 |archive-date=1 May 2023 |archive-url=https://web.archive.org/web/20230501180207/https://www.nxp.com/files-static/dsp/doc/ref_manual/MCIMX51RM.pdf |url-status=dead }} It especially supports [DDR2 SDRAM](/source/DDR2_SDRAM) at 200 MHz. The imx51 family was launched in 2009. * i.MX515 (consumer/industrial) = 800 MHz ARM Cortex A8 platform (600 MHz for industrial) + HD VPU + 3D GPU + 2.5D GPU + IPU + security * i.MX513 (consumer/industrial) = 800 MHz ARM Cortex A8 platform (600 MHz for industrial) + HD VPU + IPU * i.MX512 (consumer/industrial) = 800 MHz ARM Cortex A8 platform (600 MHz for industrial) + IPU * i.MX516 (automotive) = 600 MHz ARM Cortex A8 platform + HD VPU + 3D GPU + 2.5D GPU + IPU + security block * i.MX514 (automotive) = 600 MHz ARM Cortex A8 platform + 3D GPU + 2.5D GPU + IPU + security block ===i.MX 50 family=== thumb|Freescale MCIMX507CVM8B The i.MX508 processor is the result of Freescale collaboration with [E Ink](/source/E_Ink). It is dedicated for eReaders. Launched in 2010, it integrates the E Ink display controller within the silicon to save both BOM cost and space on the [PCB](/source/Printed_circuit_board). It especially supports LP-DDR2 SDRAM at 400 MHz. * i.MX507 (consumer) = ARM Cortex A8 platform + E Ink display controller. Builds on the i.MX508.[https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-mature-processors/multimedia-applications-processors-low-power-optimization-integrated-electronic-paper-display-epd-arm-cortex-a8-core:i.MX507 Freescale i.MX507] * i.MX508 (consumer) = 800 MHz ARM Cortex A8 platform + 2.5D GPU + Pixel Pipeline + E Ink display controller. ===i.MX 53 family=== i.MX535 was announced in June 2010. Shipped since the first quarter of 2011. * i.MX537 (industrial) = 800 MHz ARM Cortex A8 platform + Full HD VPU (1080p decode) + 3D GPU + 2.5D GPU + IPU + security + IEEE1588 * i.MX535 (consumer) = 1 GHz ARM Cortex A8 platform + Full HD VPU (1080p decode) + 3D GPU + 2.5D GPU + IPU + security * i.MX536 (automotive) = 800 MHz ARM Cortex A8 platform + Full HD VPU (1080p decode) + 3D GPU + 2.5D GPU + IPU + security * i.MX534 (automotive) = 800 MHz ARM Cortex A8 platform + 3D GPU + 2.5D GPU + IPU + security ==i.MX 6 series== The i.MX 6 series are based on the [ARM Cortex A9](/source/ARM_Cortex-A9_MPCore) solo, dual or quad cores (in some cases [Cortex A7](/source/Cortex_A7)) and typically comes with one or more [Vivante](/source/Vivante) GPUs. It is designed in the 40 nm process. i.MX 6 Solo, Dual and Quad were announced in January 2011, during [Consumer Electronics Show](/source/Consumer_Electronics_Show) in Las Vegas. {| class="wikitable" |- ! Name ! Clock speed ! CPU cores ! L2 cache
in kB ! Embedded
SRAM in kB ! 3D GPU / shaders /
shader clock in MHz ! 2D GPU ! Vector GPU ! VPU ! other graphics cores ! other cores |- ! i.MX 6 ULL | 528 MHz
(Cortex-A7) | 1 | 128 | 128 | | | | | {{partial|1× PXP}} | security |- ! i.MX 6 UltraLite | 528/696 MHz
(Cortex-A7) | 1 | 128 | 128 | | | | | {{partial|1× PXP}} | security |- ! {{anchor|SLL}}i.MX 6 SLL{{cite web|url=https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6sll-processors-single-core-processor-with-arm-cortex-a9-core:i.MX6SLL |title=i.MX 6SLL Processors - Single-Core Processor with Arm® Cortex®-A9 Core |website=NXP.com |access-date=2019-11-03}} | 800 MHz/1.0 GHz | 1 | 256 | 128 | | | | | {{partial|1× PXP}} | security |- ! {{anchor|SoloLite}}i.MX 6 SoloLite | 1.0 GHz | 1 | 256 | 128 | | Vivante GC320 | Vivante GC355 | | {{partial|1× PXP}} | security |- ! i.MX 6 SoloX | 1.0 GHz | 1 | 256 | 128 | {{partial|Vivante GC400T}} / 1 / 720 | Vivante GC320 | Vivante GC355 | | {{partial|1× PXP}} | Cortex-M4 core, security |- ! i.MX 6 Solo | 1.0 GHz | 1 | 512 | 128 | {{partial|Vivante GC880}} / 1 / 528 | Vivante GC320 | | Full HD (1080p decode) | {{good|1× IPUv3, 1× PXP}} | security |- ! i.MX 6 DualLite | 1.0 GHz | 2 | 512 | 128 | {{partial|Vivante GC880}} / 1 / 528 | Vivante GC320 | | Full HD (1080p decode) | {{good|1× IPUv3, 1× PXP}} | security |- ! i.MX 6 Dual | 1.2 GHz | 2 | 1024 | 256 | {{good|Vivante GC2000}} / 4 / 594 | Vivante GC320 | Vivante GC355 | Full HD (1080p decode) | {{yes|2× IPUv3}} | security |- ! i.MX 6 Quad | 1.2 GHz | 4 | 1024 | 256 | {{good|Vivante GC2000}} / 4 / 594 | Vivante GC320 | Vivante GC355 | dual Full HD (1080p decode) | {{yes|2× IPUv3}} | security |- ! i.MX 6 DualPlus | 1.0 (1.2) GHz | 2 | 1024 | 512 | {{yes|Vivante GC3000}} / 4 / 720 | Vivante GC320 | Vivante GC355 | Full HD (1080p decode) | {{yes|2× IPUv3}} | security |- ! i.MX 6 QuadPlus | 1.0 (1.2) GHz | 4 | 1024 | 512 | {{yes|Vivante GC3000}} / 4 / 720 | Vivante GC320 | Vivante GC355 | dual Full HD (1080p decode) | {{yes|2× IPUv3}} | security |} * "Plus" versions with 1.2 GHz are currently only available via special request to NXP.{{cite web|url=http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/i.mx6qp/i.mx-6quadplus-processor-quad-core-high-performance-advanced-3d-graphics-hd-video-advanced-multimedia-arm-cortex-a9-core:i.MX6QP |title=i.MX6QP|i.MX 6QuadPlus Processors|Quad Core |website=NXP.com |access-date=2016-09-24}} * Vivante GC2000 achieves ~19 G[FLOPS](/source/FLOPS) for a 594 MHz shader clock and ~23 GFLOPS for a 720 MHz shader clock. ==i.MX 7 series== The i.MX 7 series is based on the low-power [ARM Cortex A7](/source/ARM_Cortex-A7) CPU core with a secondary ARM Cortex M4 real-time co-processor. It is designed 28 nm fully depleted [silicon on insulator](/source/silicon_on_insulator) (FDSOI) process.{{cite web|url=http://www.eetimes.com/document.asp?doc_id=1325866 |title=Freescale, Cisco, Ciena Give Nod to FD-SOI |publisher=EE Times |access-date=2016-09-24}} Only low-powered single and dual-core models, designed for [IoT](/source/Internet_of_Things) applications, have been released. i.MX 7Solo and i.MX 7Dual were announced in September 2013.{{cite web|url=http://www.cnx-software.com/2015/06/23/freescale-launches-i-mx-7-series-cortex-a7-cortex-m4-processors-for-iot-applications/ |title=Freescale Launches i.MX 7 Series Cortex A7 + Cortex M4 Processors for IoT Applications |website=Cnx-software.com |date=2015-06-23 |access-date=2016-09-24}}{{cite web|url=http://www.nxp.com/files/training/doc/dwf/DWF13_APF_CON_T0838.pdf |title=Archived copy |access-date=2016-02-23 |url-status=dead |archive-url=https://web.archive.org/web/20160304040324/http://www.nxp.com/files/training/doc/dwf/DWF13_APF_CON_T0838.pdf |archive-date=2016-03-04 }} {| class="wikitable" |- ! Name ! Clock speed (MHz) ! CPU cores ! L2 cache (KB) ! 3D GPU ! 2D GPU ! Vector GPU ! VPU ! other graphics cores ! other cores |- ! i.MX 7Solo | 800 | 1 | 512 | - | - | - | - | PXP | Secondary CPU – ARM Cortex M4 real-time co-processor |- ! i.MX 7Dual | 1000 | 2 | 512 | - | - | - | - | PXP | Secondary CPU – ARM Cortex M4 real-time co-processor |} ==i.MX 8 series== There are four major different series of the i.MX 8: * i.MX 8 series * i.MX 8M series, * i.MX 8ULP series, * i.MX 8X series. Each series differs significantly from each other and are not pin compatible. Within each series some versions are pin compatible. Each series also has a suffix such as Quad, Dual, Plus, Max or a combination thereof, for example: QuadMax or DualPlus. The i.MX 8 series has many variants but it is not clear how the name corresponds to a feature set. In previous CPU series the naming convention clearly corresponds to a function or feature set, but this is not the case with i.MX 8. The i.MX 8 series was announced in September 2013 and is based on the [ARMv8-A](/source/ARMv8-A) [64-bit](/source/64-bit) CPU architecture. According to NXP, the i.MX 8 series is designed for Driver Information Systems (car computers) and applications have been released. In May 2016 the i.MX 8 became available as a multisensory enablement kit (MEK) based on i.MX 8.{{cite web|url=http://media.nxp.com/phoenix.zhtml?c=254228&p=irol-newsArticle&ID=2168969 |title=NXP Semiconductors :: Press Release |website=Media.nxp.com |date=2016-05-17 |access-date=2016-09-24}}{{cite web|url=http://www.nxp.com/pages/i.mx-8-multisensory-enablement-kit:i.MX8-MEK?tid=vaniMX8-MEK |title=i.MX 8 Multisensory Enablement Kit |website=NXP.com |access-date=2016-09-24}}{{cite web|url=http://www.cnx-software.com/2016/05/17/nxp-unveiled-i-mx-8-multisensory-enablement-kit-with-hexa-core-armv8-processor/ |title=NXP Unveils i.MX 8 Multisensory Enablement Kit with Hexa Core ARMv8 Processor |website=Cnx-software.com |date=2016-05-17 |access-date=2016-09-24}} Slides from NXP FTF found on the web {{cite web|url=http://news.mynavi.jp/photo/articles/2016/05/18/nxpftf2016_imx8/images/100l.jpg |title=拡大画像 013 | 【レポート】NXP FTF 2016 - 28nm FD-SOIで製造されるi.MX 8 (1) FTFがNX…… | マイナビニュース |website=News.mynavi.jp |date= 18 May 2016|access-date=2016-09-24}} indicated an initial total of 5 variants (with a main level of categorization into "Dual" and "Quad") with varying the CPU and GPU capabilities. The CPU was suggested to include varying counts of [Cortex-A72](/source/Cortex-A72), [Cortex-A53](/source/Cortex-A53) and [Cortex-M4](/source/Cortex-M4), while the GPU is either 1 or 2 units of the [Vivante](/source/Vivante) GC7000VX. Other publications supported this general image, some even including photos of an evaluation kit that is named "Multisensory Enablement Kit" (MEK) that got later promoted as a development support product by NXP. The i.MX 8 was announced Q1 2017, based around 3 products.{{cite web|title=i.MX 8 Factsheet|url=http://www.nxp.com/files/32bit/doc/fact_sheet/IMX8FAMFS.pdf?fasp=1&WT_TYPE=Fact%20Sheets&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf|website=NXP|access-date=6 October 2016|archive-date=9 October 2016|archive-url=https://web.archive.org/web/20161009115353/http://www.nxp.com/files/32bit/doc/fact_sheet/IMX8FAMFS.pdf?fasp=1&WT_TYPE=Fact%20Sheets&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf|url-status=dead}} Two variants include four [Cortex-A53](/source/Cortex-A53). All versions includes one or two [Cortex-A72](/source/Cortex-A72) CPU cores and all versions includes two [Cortex-M4F](/source/ARM_Cortex-M) CPU cores. All i.MX 8 [SoCs](/source/System_on_a_chip) include Vivante GC7000 Series GPUs. The QuadPlus is using GC7000Lite cores, while the 'QuadMax' includes two full GC7000 GPUs. {| class="wikitable" |- ! Name ! Clock speed (MHz) ! CPU cores ! L2 cache ! GPU ! VPU ! Other cores |- ! i.MX 8 QuadMax | 1.2 GHz + 1.6 GHz {{Cite web|url=https://www.nxp.com/docs/en/application-note/AN12060.pdf|title=Software ISP Application Note, Chapter 3.2}} | 4× [Cortex-A53](/source/Cortex-A53) + 2× [Cortex-A72](/source/Cortex-A72) | 2× 1 MB | 2× [Vivante](/source/Vivante) GC7000/XSVX |[H.265](/source/H.265) decode [4K](/source/4k_resolution)/2K, [H.264](/source/H.264) encode/decode [1080p](/source/1080p) | 2× [Cortex-M4F](/source/Cortex-M4) (266 MHz) |- ! i.MX 8 QuadPlus | 1.2 GHz + 1.6 GHz | 4× [Cortex-A53](/source/Cortex-A53) + 1× [Cortex-A72](/source/Cortex-A72) | 2× 1 MB | 2× Vivante GC7000Lite/XSVX |[H.265](/source/H.265) decode [4K](/source/4k_resolution)/2K, [H.264](/source/H.264) encode/decode [1080p](/source/1080p) | 2× [Cortex-M4F](/source/Cortex-M4) (266 MHz) |- ! i.MX 8 DualMax | 1.6 GHz | 2× [Cortex-A72](/source/Cortex-A72) | 1 MB | 1× Vivante GC7000/XSVX |[H.265](/source/H.265) decode [4K](/source/4k_resolution)/2K, [H.264](/source/H.264) encode/decode [1080p](/source/1080p) | 2× [Cortex-M4F](/source/Cortex-M4) (266 MHz) |} '''Standard Key Features:''' Advanced Security, Ethernet with AVB, USB 3.0 with PHY, MMC/SDIO, UART, SPI, I²C, I²S, Timers, Secure RTC, Media Processor Engine (Neon™), Integrated Power Management. {| class="wikitable" ! ! colspan="7" |CPU, GPU and DSP ! colspan="4" |HMI & Multimedia ! colspan="4" |GPU Libraries and Extensions ! colspan="2" |Interfaces ! colspan="4" |Memory Types |- !Product Family !{{verth|Cortex-A72}} !{{verth|Cortex-A53}} !{{verth|Cortex-A35}} !{{verth|Cortex-M4F}} !{{verth|Cortex-M33}} !{{verth|DSP}} !{{verth|GPU}} !{{verth|Display Resolution and Interfaces:
MIPI-DSI / Parallel / HDMI}} !{{verth|Camera Interfaces:
MIPI-CSI / Parallel / HDMI}} !{{verth|Video Decode Resolution
(Top Codecs)}} !{{verth|Video Encode Resolution
(Top Codecs)}} !{{verth|OpenVX (vision)}} !{{verth|OpenGL ES}} !{{verth|OpenCL}} !{{verth|Vulkan}} !{{verth|PCIe}} !{{verth|Gigabit Ethernet}} !{{verth|LPDDR4}} !{{verth|DDR4}} !{{verth|DDR3L}} !{{verth|ECC option}} |- |'''i.MX 8''' Advanced Graphics, Performance and Virtualization |2 |4 | |2 | |1 |2 |4k + 1080p 2 / 1 / 1 |2 / 2 / 1 |4K (h.265, h.264) |1080p60 (h.264) |{{Yes|Yes}} |3.1 |2.0 |{{Yes|Yes}} |2 |2x |{{Yes|Yes}} |{{Yes|Yes}} | | |- |'''i.MX 8M''' Advanced Audio, Voice and Video | |4 | |1 | | |1 |4k + 1080p 1 / 0 / 1 |2 / 0 / 0 |4Kp60 with High Dynamic Range (h.265, VP9); 4Kp30 (h.264, VP8) |1080p30 (h.264) - SW | |3.1 |1.2 |{{Yes|Yes}} |2 |1x |{{Yes|Yes}} |{{Yes|Yes}} |{{Yes|Yes}} | |- |'''i.MX 8M Mini''' Embedded Consumer and Industrial Applications | |4 | |1 | | |1 |1080p 1 / 0 / 0 |1 / 0 / 0 |1080p60 (h.265, VP9, h.264, VP8) |1080p60 (h.264) | |2.0 | | |1 |1x |{{Yes|Yes}} |{{Yes|Yes}} |{{Yes|Yes}} | |- |'''*i.MX 8ULP''' Industrial, Mobile and Smart Home Applications | | |2 | |1 |1 |2 | 1 / 1 / 0 |1 / 1 / 0 | | | |3.1 |Yes |{{Yes|Yes}} |0 |0x |{{Yes|Yes}} | | | |- |'''*i.MX 8ULP-CS''' Cloud Secured for IoT and Industrial Applications | | |1 | |1 |1 |1 | 1 / 1 / 0 |1 / 1 / 0 | | | | | |{{No|No}} |0 |0x |{{Yes|Yes}} | | | |- |'''i.MX 8X''' Safety certifiable and efficient performance | | |4 |1 | |1 |1 |4K or 2x 1080p 2 / 1 / 0 |1 / 1 / 0 |4K (h.265); 1080p60 (h.264, VP8) |1080p30 (h.264) | |3.1 |1.2 EP |{{Yes|Yes}} |1 |2x |{{Yes|Yes}} | |{{Yes|Yes}} |{{Yes|Yes}} |} *pre-production === i.MX 8 === {| class="wikitable" !Feature ! colspan="3" |ARM core !DSP !GPU !PCIe 3.0 |- |i.MX 8 QuadMax |2× Cortex-A72 | rowspan="2" |4× [Cortex-A53](/source/Cortex-A53) | rowspan="2" |2× [Cortex-M4F](/source/ARM_Cortex-M) | rowspan="2" |HiFi 4 DSP |2 x GC7000XSVX |1x (2-lane) |- |i.MX 8 QuadPlus |1× Cortex-A72 |2 x GC7000Lite/XSVX |1x (1-lane) |} ===i.MX 8M=== The i.MX 8M series were announced on January 4 at CES 2017.{{Cite web|url=http://media.nxp.com/phoenix.zhtml?c=254228&p=irol-newsArticle&ID=2233904|title=NXP Semiconductors :: Press Release|website=media.nxp.com|access-date=2017-04-09}} Main features:{{Cite web|url=http://www.nxp.com/assets/documents/data/en/fact-sheets/i.MX8M-FS.pdf|title=i.MX 8M Fact Sheet}} * Up to four 1.5 GHz [ARM Cortex-A53](/source/ARM_Cortex-A53) processors * [Cortex-M4F](/source/ARM_Cortex-M) for real-time processing * LPDDR4, [DDR4](/source/DDR4) and [DDR3](/source/DDR3)(L) memory support * Two [USB](/source/USB) 3.0 interfaces with PHY and Type-C support * Two PCIe interfaces (1-lane each) with L1 substates for fast wakeup and low power * [HDMI](/source/HDMI) 2.0a and MIPI-DSI (4-lane) display interfaces • Up to two MIPI-CSI2 (4-lane) camera interfaces * Gigabit Ethernet MAC with Audio Video Bridging (AVB) and EEE capability * [4K](/source/Ultra-high-definition_television) UltraHD resolution and 10-bit High Dynamic Range (HDR) in H.264, H.265 and VP9 support * Up to 4Kp60 resolution on the HDMI 2.0a output and 1080p60 resolution on the MIPI-DSI (4-lanes) interface * [OpenGL ES](/source/OpenGL_ES) 3.1, [OpenCL](/source/OpenCL) 1.2, [OpenGL](/source/OpenGL) 3.0, [OpenVG](/source/OpenVG) and [Vulkan](/source/Vulkan_(API)) support {| class="wikitable" !Feature !ARM core !ARM core !Audio !GPU !VPU !Camera |- |i.MX 8M Dual |2× 1.5 GHz [Cortex-A53](/source/Cortex-A53) | rowspan="4" |1× [Cortex-M4F](/source/ARM_Cortex-M) | rowspan="4" |20 channels in/out; 32-bit up to 384 kHz, with DSD512 support | rowspan="3" |GC7000Lite | rowspan="2" |4Kp60, H.265 and VP9 | rowspan="3" |2× MIPI-CSI |- |i.MX 8M Quad | rowspan="2" |4× 1.5 GHz Cortex-A53 |- |i.MX 8M QuadLite | rowspan="2" | - |- |i.MX 8M Solo |1× 1.5 GHz [Cortex-A53](/source/Cortex-A53) |GC7000nanoULTRA | - |} === i.MX 8M Mini === The i.MX 8M Mini is NXP's first embedded multi-core heterogeneous applications processors built using 14LPC FinFET process technology. At the heart is a scalable core complex of up to four Arm Cortex-A53 cores running up to 2 GHz plus Cortex-M4 based real-time processing domain at 400+MHz. i.MX 8M Mini core options are used for consumer, audio, industrial, machine learning training and inferencing across a range of cloud providers. '''Features'''{{Cite web|url=https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-mini-family-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI|title=i.MX 8M Mini Applications Processor {{!}} Arm Cortex-A53, Cortex-M4{{!}}NXP|website=www.nxp.com|access-date=2018-03-13}} * Heterogeneous Multi-core Processing Architecture * Quad-core Arm Cortex-A53 core up to 2 GHz * Cortex-M4 at speeds of 400+MHz * 1080p video encode and decode * 2D and 3D graphics * Display and camera interfaces * Multi-channel audio and digital microphone inputs * Connectivity (I2C, SAI, UART, SPI, SDIO, USB, PCIe, Gigabit Ethernet) * Low-power and standard DDR memory support * Multiple pin-compatible product offerings * Consumer and Industrial {| class="wikitable" !Feature !ARM core !ARM core !DRAM !Audio !GPU !Video Decode !Video Encode !Display !Camera !USB with PHY |- |i.MX 8M Mini | rowspan="2" |1×, 2× or 4× [Cortex-A53](/source/Cortex-A53) | rowspan="2" |1× [Cortex-M4F](/source/ARM_Cortex-M) | rowspan="2" |32-bit LPDDR4/DDR4/DDR3(L) | rowspan="2" |20x I2S 32-bit up to 384 kHz with DSD512 and TDM support 8-ch PDM microphone inputs | rowspan="2" |3D: GCNanoUltra 2D: GC320{{Cite web|title=AN12296 - i.MX 8M Mini Migration Guide|url=https://www.nxp.com/docs/en/application-note/AN12296.pdf|access-date=2021-09-29}} |1080p60 H.265, H.264, VP8, VP9 |1080p60 H.264, VP8 | rowspan="2" |1x MIPI-DSI | rowspan="2" |1x MIPI-CSI | rowspan="2" |1x PCIe 2.0 3x SDIO/eMMC 2x USB 2.0 1x GbE |- |i.MX 8M Mini Lite | - | - |} === i.MX 8X === The i.MX 8X series were announced on March 14, 2017.{{Cite web|url=http://media.nxp.com/phoenix.zhtml?c=254228&p=irol-newsArticle&ID=2253814|title=NXP Semiconductors :: Press Release|website=media.nxp.com|access-date=2017-04-09}} Main features:{{Cite web|url=http://www.nxp.com/assets/documents/data/en/fact-sheets/IMX8XFAMFS.pdf|title=i.MX 8X Fact Sheet}} * Up to four 1.2 GHz [Cortex-A35](/source/Cortex-A35) processors * [Cortex-M4F](/source/ARM_Cortex-M) for real-time processing * Latest cryptography standards ([AES](/source/Advanced_Encryption_Standard), flashless SHE, elliptical curve cryptography, key storage) * [ECC memory](/source/ECC_memory) * Tensilica HiFi 4 DSP for audio pre- and post- processing, key word detection and speech recognition * 28 nm FD-SOI process {| class="wikitable" !Feature !ARM core !ARM core !DSP Core ! colspan="2" |DRAM !GPU !VPU !Ethernet !USB with PHY |- |i.MX 8 QuadXPlus |4× 1.2 GHz [Cortex-A35](/source/Cortex-A35) | rowspan="3" |1× [Cortex-M4F](/source/ARM_Cortex-M) | rowspan="3" |Tensilica HiFi 4 DSP | rowspan="2" |32-bit | rowspan="3" |DDR3L (ECC option) LPDDR4 (no ECC) | rowspan="2" |GC7000Lite | rowspan="2" |4K H.265 dec 1080p H.264 enc/dec | rowspan="2" |2× gigabit with AVB | rowspan="2" |1× USB 3.0 1× USB 2.0 |- |i.MX 8 DualXPlus | rowspan="2" |2× 1.2 GHz Cortex-A35 |- |i.MX 8 DualX |16-bit |GC7000UltraLite |1080p H.264 enc/dec |1× gigabit with AVB 1× 10/100 |2× USB 2.0 |} == i.MX 9 series ==
The i.MX 9 series represents NXP's latest generation of application processors, built on advanced manufacturing processes and featuring [ARM Cortex-A55](/source/ARM_Cortex-A55) cores. The series was developed to address growing demands for edge computing, real-time connectivity, and AI/ML capabilities in industrial, automotive, and IoT applications. The i.MX 9 family includes multiple variants (i.MX 91, i.MX 93, i.MX 94, i.MX 95) targeting different market segments and performance requirements. Main features:{{Cite web |title=i.MX 9 Applications Processors |url=https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors:IMX9-PROCESSORS |access-date=2025-11-15 |website=www.nxp.com}} * ARM Cortex-A55 cores (1 to 6 cores depending on variant) * ARM Cortex-M33 or Cortex-M7 co-processors for real-time processing * Neural Processing Unit (NPU) on select variants for AI/ML acceleration * Time-Sensitive Networking (TSN) support for industrial and automotive applications * Post-quantum cryptography (PQC) on i.MX 94 for quantum-resistant security * Advanced display support (up to 4K30p on i.MX 95) * LPDDR4/LPDDR4X memory with ECC support * PCIe Gen 3.0, USB 2.0/3.0, Gigabit/10 Gigabit Ethernet connectivity * Multiple CAN-FD interfaces for automotive and industrial applications * Hardware security features including secure boot and memory encryption {| class="wikitable" ! ! colspan="7" |CPU and other processors ! colspan="2" |HMI & Multimedia ! colspan="10" |Interfaces ! colspan="2" |Memory Types |- !Product Family !{{verth|Cortex-A55}} !{{verth|Cortex-M33}} !{{verth|Cortex-M7}} !{{verth|DSP}} !{{verth|NPU}} !{{verth|GPU}} !{{verth|ISP}} !Display Resolution and Interfaces !Camera Resolution and Interfaces !{{verth|PCIe}} !{{verth|USB 2.0}} !{{verth|USB 3.0}} !{{verth|Ethernet}} !{{verth|External Memory}} !{{verth|CAN-FD}} !{{verth|UART}} !{{verth|Flex - IO}} !{{verth|Audio}} !{{verth|Others}} !{{verth|LPDDR4 (with ECC)}} !{{verth|LPDDR4X (with ECC)}} |- |i.MX 91 |1 | | | | | | |24 bit-per-pixel parallel RGB/YUV Display |8-bit parallel RGB/YUV Camera | |2x USB 2.0 (Dual mode, w/Type C) | |2x 1GbE (1 w/TSN) |3x SD/SDIO3.0/eMMC5.1, 1x Octal SPI |2 |8 |2x 32-pin |3 SAI (1 2-lane, 2-1 lane)/ 4x I2S TDM (32-bit @ 384 kHz) 8 channel PDM microphone input + Medium Quality Sound output, SPDIF |1x 4-ch, 12-bit ADC, 8x I2C, 8x SPI, 2x I3C XSPI responder | | |- |i.MX 93ML |2 |1 | | |1 |2D | |1080p60 MIPI DSI (4-lane), 720p60 LVDS (4-lane), 24-bit parallel RGB |1080p60 MIPI CSI (2-lane), 8-bit parallel YUV/RGB | |2 | |2x 1GbE with 1 w/TSN |3x SD/SDIO3.0/eMMC5.1, 1x Octal SPI |2 |8 |2x 32-bit |7x I2S, SPDIF, PDM mic, MQS output |4-ch 12-bit ADC, 8x I2C, 2x I3C, 8x SPI | | |- |i.MX 95 |Up to 6 |1 |1 |Immersiv3D™ Audio Framework |1 |3D |1 |4K30P, 3840x1440P60 MIPI-DSI (4-lane) Up to 1080P LVDS (2x 4-lane or 1x 8-lane) |2x4kp30, 4x1080p60, 8x1080p30 MIPI-CSI (2x 4-lane) |2 Gen 3.0 (1-lane) |1 |1 |10 GbE + 2x 1 GbE with 1x TSN |3x SD/SDIO3.0/eMMC5.1, 1x Octal SPI |}
== i.MX RT series == The i.MX RT series represents a crossover between traditional microcontrollers and application processors, combining the real-time capabilities and deterministic performance of microcontrollers with the higher clock speeds and peripheral sets typically found in applications processors. Unlike traditional microcontrollers that rely on [flash memory](/source/flash_memory) for program storage, the i.MX RT series uses large amounts of integrated [SRAM](/source/Static_random-access_memory) as the primary program execution space. This architectural choice eliminates wait states associated with flash memory access, enabling the processors to achieve higher sustained performance and more deterministic execution times crucial for real-time applications.{{Cite web |last=N.V |first=NXP Semiconductors |date=2017-10-24 |title=NXP's i.MX RT Crossover Processor Sets Highest Microcontroller Real-Time Benchmark Performance Yet |url=https://www.globenewswire.com/news-release/2017/10/24/1152547/32283/en/NXP-s-i-MX-RT-Crossover-Processor-Sets-Highest-Microcontroller-Real-Time-Benchmark-Performance-Yet.html |access-date=2025-11-15 |website=GlobeNewswire News Room |language=en-us}} The RT series targets [edge computing](/source/edge_computing), [industrial automation](/source/industrial_automation), [IoT devices](/source/Internet_of_things), and other applications requiring real-time responsiveness combined with higher processing power than conventional microcontrollers can provide. They were introduced at up to 600 MHz on a 40 nm node, which was later upgraded to 1 GHz on a 28 nm node. The inaugural device from this series was the i.MX RT1050, introduced in the fall of 2017. As of 2025, the family consists of Cortex-M7 devices (400 MHz to 1 GHz) and Cortex-M33 devices (200-325 MHz) targeting different performance and power requirements.{{Cite web |title=i.MX RT Series: MCU/Applications Crossover MCUs {{!}} Arm® Cortex®-M7 |url=https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus:IMX-RT-SERIES |access-date=2025-11-15 |website=www.nxp.com}} Main features:{{cite web |last1= |date=n.d. |title=First GHz MCU with Arm Cortex-M7 and Cortex-M4 Cores |url=https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170 |access-date=17 August 2020 |website=nxp.com |publisher=[NXP Semiconductors](/source/NXP_Semiconductors)}} * ARM Cortex-M7 cores (400 MHz to 1 GHz){{cite web |last1=Turley |first1=Jim |date=8 October 2019 |title=NXP MCU Hits 1 GHz |url=https://www.eejournal.com/article/nxp-mcu-hits-1-ghz/ |access-date=17 August 2020 |website=eejournal.com |publisher=Electronics Engineering Journal}} or ARM Cortex-M33 cores (200-325 MHz) * Zero-wait-state code execution from on-chip SRAM * Hardware acceleration for graphics, cryptography, and signal processing * FlexSPI interfaces for external memory (QSPI/Octal SPI flash, SDRAM) * Advanced connectivity (USB 2.0/3.0, Gigabit Ethernet with TSN/AVB, CAN-FD) * Security features including secure boot, TrustZone-M, and crypto accelerators * 2D graphics acceleration and display controllers (MIPI-DSI, parallel RGB, LVDS) * [Audio processing](/source/Audio_signal_processing) with DSP coprocessors (Cadence Tensilica HiFi 1/4, Fusion F1) * Neural Processing Unit (NPU) on RT700 series for AI/ML acceleration * Real-time operating system support (FreeRTOS, Zephyr, Azure RTOS) The i.MX RT1170 represents the high-performance flagship with dual cores (Cortex-M7 at 1 GHz and Cortex-M4 at 400 MHz) running in separate power domains. It includes two Gigabit Ethernet ports with Time-Sensitive Networking (TSN) support and achieves over 4,500 CoreMark performance. The RT1160 offers similar dual-core architecture with three Ethernet interfaces. The i.MX RT500 series, introduced in 2021, marked the entry into ultra-low-power crossover MCUs with ARM Cortex-M33 at 275 MHz paired with a [Cadence](/source/Cadence_Design_Systems) Xtensa Fusion F1 DSP, optimized for [wearables](/source/wearables) and IoT applications with up to 5 MB SRAM.{{Cite web |last=Das |first=Debashis |date=2024-09-27 |title=NXP i.MX RT700 dual-core Cortex-M33 AI Crossover MCU includes eIQ Neutron NPU and DSPs - CNX Software |url=https://www.cnx-software.com/2024/09/27/nxp-i-mx-rt700-dual-core-cortex-m33-ai-crossover-mcu-includes-eiq-neutron-npu-and-dsps/ |access-date=2025-11-15 |website=CNX Software - Embedded Systems News |language=en-US}} The i.MX RT600 series focuses on audio and voice applications, featuring Cortex-M33 at 300 MHz with a Cadence Tensilica HiFi 4 DSP at 600 MHz. It supports up to 8 digital microphones and includes 4.5 MB SRAM for audio processing workloads.{{Cite web |title=i.MX RT600 {{!}} Crossover MCU with ARM Cortex-M33 and DSP Core |url=https://www.nxp.com/products/i.MX-RT600 |access-date=2025-11-15 |website=www.nxp.com}} Announced in September 2024, the i.MX RT700 introduces integrated AI acceleration through an eIQ Neutron NPU.{{Cite web |last=Das |first=Debashis |date=2024-09-27 |title=NXP i.MX RT700 dual-core Cortex-M33 AI Crossover MCU includes eIQ Neutron NPU and DSPs - CNX Software |url=https://www.cnx-software.com/2024/09/27/nxp-i-mx-rt700-dual-core-cortex-m33-ai-crossover-mcu-includes-eiq-neutron-npu-and-dsps/ |access-date=2025-11-15 |website=CNX Software - Embedded Systems News |language=en-US}} It features up to five cores including dual [Cortex-M33](/source/Cortex-M33) processors (325 MHz and 250 MHz), HiFi 4 and HiFi 1 DSPs, and a RISC-V based I/O coprocessor. The NPU provides up to 100x AI performance acceleration with 30% reduced active power and 70% improved sleep mode efficiency compared to earlier RT series.{{Cite web |title=NXP Unveils the i.MX RT700 Microcontroller, Promises Near-Two Hundred Times the Edge AI Performance |url=https://www.hackster.io/news/nxp-unveils-the-i-mx-rt700-microcontroller-promises-near-two-hundred-times-the-edge-ai-performance-11cdbe73fe3e |access-date=2025-11-15 |website=Hackster.io |language=en}} The RT700 is expected to begin sampling in Q1 2025.{{Cite web |title=NXP Unwraps Crossover MCU Aimed at the AI-Enabled Edge - News |url=https://www.allaboutcircuits.com/news/nxp-unwraps-crossover-mcu-aimed-at-the-ai-enabled-edge/ |access-date=2025-11-15 |website=www.allaboutcircuits.com |language=en}} NXP provides development support through MCUXpresso SDK and IDE, with RTOS support for [FreeRTOS](/source/FreeRTOS), [Zephyr](/source/Zephyr_(operating_system)), and [Azure RTOS](/source/Azure_RTOS). The eIQ machine learning environment supports [TensorFlow](/source/TensorFlow) Lite Micro and [PyTorch](/source/PyTorch) Glow for edge AI applications.{{cite web |last1=Wong |first1=William |date=7 August 2020 |title=Neural-Network Compiler Adds a Glow to Micros |url=https://www.electronicdesign.com/technologies/iot/article/21138631/neuralnetwork-compiler-adds-a-glow-to-micros |access-date=17 August 2020 |website=electronicdesign.com |publisher=Electronic Design}} ==Software support== Freescale proposed a layered approach of software with selection of software components optimized for its [chips](/source/Integrated_circuit). The i.MX [board support package](/source/board_support_package)s (BSP), common across all i.MX nodes, consists of kernel optimization, hardware drivers, and unit tests. The company also provides multimedia codecs (ARM and Video processing unit accelerated). i.MX also includes middleware with reuse of open source frameworks like multimedia framework plugins, power management, security/DRM, or graphics ([OpenGL](/source/OpenGL)/[OpenVG](/source/OpenVG)). ===Linux=== Freescale i.MX development kits include a Linux software stack with a [GNOME](/source/GNOME) Mobile environment. On the i.MX51 family, the reference user interface is [Ubuntu](/source/Ubuntu_(operating_system)). The last Ubuntu version supported is 10.04.1 (still available on mirrors). Ubuntu dropped the "official" i.MX51 family support since version 10.10.{{cite web|url=https://wiki.ubuntu.com/ARM/MaverickReleaseNotes |title=ARM/MaverickReleaseNotes - Ubuntu Wiki |website=Wiki.ubuntu.com |date=2011-09-23 |access-date=2016-09-24}} Since Ubuntu 11.10 support for the i.MX53 Quickstart board is available as a preinstalled desktop or server SD card.{{cite web|url=https://wiki.edubuntu.org/OneiricOcelot/ReleaseNotes#New_ARM_subarchitectures |title=OneiricOcelot/ReleaseNotes - Ubuntu Wiki |website=Wiki.edubuntu.org |access-date=2016-09-24}} The [OpenEmbedded](/source/OpenEmbedded) Linux distribution supports several i.MX platforms. Commercial Linux support is available from companies like [Lanedo](/source/Lanedo), [TimeSys](/source/TimeSys), [MontaVista](/source/MontaVista), [Wind River Systems](/source/Wind_River_Systems) and [Mentor Graphics](/source/Mentor_Graphics). ===Android=== In February 2010, Freescale launched an [Android](/source/Android_(operating_system)) platform for the i.MX5x family.{{cite web |title=Android OS for i.MX Applications Processors|NXP |url=http://www.freescale.com/imxandroid |access-date=2016-09-24 |website=Freescale.com}} ===Chromium=== In early 2010 Freescale demoed [ChromiumOS](/source/ChromiumOS) running on the i.MX515 processor.{{cite web |date=2010-03-08 |title=Chromium OS on a $199 Tablet |url=https://www.youtube.com/watch?v=Yr5cGR-uSv4 |url-status=live |archive-url=https://ghostarchive.org/varchive/youtube/20211221/Yr5cGR-uSv4 |archive-date=2021-12-21 |access-date=2016-09-24 |publisher=[YouTube](/source/YouTube)}}{{cbignore}} The company has not disclosed any further plans about Chromium or Chrome. ===FreeBSD=== Support for the Freescale i.MX51 was added to FreeBSD on 2013-03-20.{{cite web|url=http://lists.freebsd.org/pipermail/svn-src-head/2013-March/045863.html |title=Svn commit: r248557 Controller |website=Lists.freebsd.org |access-date=2016-09-24}} Support for other members of the i.MX5 family has been added since. Support for the Freescale i.MX 6 family was added to FreeBSD on 2013-10-31.{{cite web|url=http://lists.freebsd.org/pipermail/freebsd-arm/2013-November/006877.html |title=Wandboard support |website=Lists.freebsd.org |access-date=2016-09-24}} === Genode === The Operating System Framework supports the i.MX range.{{Cite web |last=Feske |first=Norman |date=May 2024 |title=Genode Foundations |url=https://genode.org/documentation/genode-foundations/index |website=Genode |page=15}} Sculpt OS is maintained for the MNT Reform family (i.MX8).{{Cite web |title=MNT Pocket Reform Sculpt 24.10 Preview Image |url=https://genodians.org/jws/2024-11-25-sculpt_mnt_pocket |access-date=2025-04-16 |website=Genodians.org |language=en}} ===NetBSD=== [NetBSD](/source/NetBSD) 6.0 comes with support for the Freescale i.MX51.{{cite web|url=https://netbsd.org/releases/formal-6/NetBSD-6.0.html |title=Announcing NetBSD 6.0 |website=Netbsd.org |access-date=2016-09-24}} In version 7.0, support for i.MX 6 based boards was added.{{cite web|url=https://blog.netbsd.org/tnf/entry/working_arm_multiprocessor_support |title=NetBSD Blog |website=Blog.netbsd.org |date=2014-11-06 |access-date=2016-09-24}} ===OpenBSD=== Support for the FreeScale's i.MX 6 series SoC was added to {{cite web|url=http://marc.info/?l=openbsd-cvs&m=137850037603645&w=2 |title='CVS: cvs.openbsd.org: src' - MARC |website=Marc.info |date=2013-09-06 |access-date=2016-09-24}} OpenBSD's head on the 2013-09-06. === Plan 9 === 9front runs on MNT Reform (i.MX8) since mid-2022.{{Cite web |date=2022-11-01 |title="9FRONT "THE GOLDEN AGE OF BALLOONING" RELEASED" |url=https://9front.org/releases/2022/10/31/0/}} ===Real-time OS=== Freescale has a range of partners providing [real-time operating system](/source/real-time_operating_system)s and software running on the i.MX processors, such as [Trinity Convergence](/source/Maxim_Integrated_Products), Adeneo, Thundersoft, Intrinsyc, [Wind River Systems](/source/Wind_River_Systems), [QNX](/source/QNX), [Green Hills](/source/Green_Hills_Software), [SYSGO](/source/SYSGO) and [Mentor Graphics](/source/Mentor_Graphics).[http://www.freescale.com/webapp/sps/site/overview.jsp?code=FWDN_CUST_EXPER_CNTR_WP]{{dead link|date=September 2016}} ===RISC OS=== i.MX support in [RISC OS](/source/RISC_OS) has been available since 2015. ===Windows CE=== Freescale i.MX development kits include [WinCE](/source/Windows_CE). === wolfSSL === [wolfSSL](/source/wolfSSL) includes support for i.MX6 following all versions after (and including) wolfSSL v3.14.0. wolfSSL also provides additional support for using the Cryptographic Assistance and Assurance Module (CAAM) on the i.MX6.{{Cite web|url=https://www.wolfssl.com/mx6-caam-integrity-os/|title=i.MX6 CAAM with Integrity OS - wolfSSL|date=2018-10-26|language=en-US|access-date=2019-01-17}} ==Reference designs== In January 2010, Freescale announced the first platform of its Smart Application Blueprint for Rapid Engineering (SABRE) series.{{Cite web |url=http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1370004&highlight= |title=Welcome to Freescale Semiconductor - Media Center - News Release |archive-url=https://archive.today/20120710042532/http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1370004&highlight= |archive-date=10 July 2012 |url-status=dead}} It is a smartbook (tablet form factor with 7" touch screen resistive), running on i.MX515. In February 2010, Freescale demoed the SABRE platform for eReaders,{{cite web|url=http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code%3DRDIMX51EREADEVSYS%26aspll%3D1 |title=Archived copy |access-date=2010-04-22 |url-status=dead |archive-url=https://web.archive.org/web/20110607122239/http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX51EREADEVSYS&aspll=1 |archive-date=2011-06-07 }} based on i.MX515. Many more reference boards are mentioned and supported through the Freescale i.MX community website. These include: * i.MX23EVK * i.MX25PDK * i.MX28EVK * MX37PDK * i.MX35PDK * i.MX51EVK * i.MX53QSB (LOCO) ==See also== * [ARM Architecture](/source/ARM_architecture_family) * [List of Freescale Microcontrollers](/source/List_of_Freescale_products) * [eBook reader](/source/Comparison_of_e-book_readers) * [Automotive infotainment](/source/In_car_entertainment) * [Chumby](/source/Chumby) * [Device tree](/source/Device_tree) * [Smartbook](/source/Smartbook) * [System on a chip](/source/System_on_a_chip) ==References== {{Reflist|30em}} {{ARM-based chips}} {{Microcontrollers}} {{Motorola microcontrollers}} {{NXP Semiconductors}} {{DEFAULTSORT:I.Mx}} Category:ARM-based microcontrollers Category:NXP Semiconductors microcontrollers Category:Freescale Semiconductor microcontrollers --- Adapted from the Wikipedia article [I.MX](https://en.wikipedia.org/wiki/I.MX) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/I.MX?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.