# Hyper-threading

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Proprietary simultaneous multithreading implementation by Intel

In this high-level depiction of HTT, instructions are fetched from RAM (differently colored boxes represent the instructions of four different [processes](/source/Process_(computing))), decoded and reordered by the front end (white boxes represent [pipeline bubbles](/source/Pipeline_stall)), and passed to the execution core capable of executing instructions from two different programs during the same [clock cycle](/source/Clock_cycle).[1][2][3]

**Hyper-threading** (officially called **Hyper-Threading Technology** or **HT Technology** and abbreviated as **HTT** or **HT**) is [Intel](/source/Intel)'s [proprietary](/source/Proprietary_hardware) [simultaneous multithreading](/source/Simultaneous_multithreading) (SMT) implementation used to improve [parallelization of computations](/source/Parallel_computation) (doing multiple tasks at once) performed on [x86](/source/X86) microprocessors. It was introduced on [Xeon](/source/Xeon) server [processors](/source/Central_processing_unit) in February 2002 and on [Pentium 4](/source/Pentium_4) desktop processors in November 2002.[4] Since then, Intel has included this technology in [Itanium](/source/Itanium), [Atom](/source/Intel_Atom), and [Core series](/source/Intel_Core) CPUs, among others.[5]

For each [processor core](/source/Processor_core) that is physically present, the [operating system](/source/Operating_system) addresses two virtual (logical) cores and shares the workload between them when possible. The main function of hyper-threading is to increase the number of independent instructions in the pipeline; it takes advantage of [superscalar](/source/Superscalar_processor) architecture, in which multiple instructions operate on separate data [in parallel](/source/Parallel_computing). With HTT, one physical core appears as two processors to the operating system, allowing [concurrent](/source/Concurrent_computing) scheduling of two processes per core. In addition, two or more processes can use the same resources: If resources for one process are not available, then another process can continue if its resources are available.

In addition to requiring simultaneous multithreading support in the operating system, hyper-threading can be properly utilized only with an operating system specifically optimized for it.[6]

## Overview

A 3 GHz model of the Intel Pentium 4 processor that incorporates Hyper-Threading Technology[7]

Hyper-Threading Technology is a form of simultaneous [multithreading](/source/Multithreading_(computer_architecture)) technology introduced by Intel, while the concept behind the technology has been patented by [Sun Microsystems](/source/Sun_Microsystems). Architecturally, a processor with Hyper-Threading Technology consists of two logical processors per core, each of which has its own processor architectural state. Each logical processor can be individually halted, interrupted or directed to execute a specified thread, independently from the other logical processor sharing the same physical core.[8]

Unlike a traditional dual-processor configuration that uses two separate physical processors, the logical processors in a hyper-threaded core share the execution resources. These resources include the execution engine, caches, and system bus interface; the sharing of resources allows two logical processors to work with each other more efficiently, and allows a logical processor to borrow resources from a stalled logical core (assuming both logical cores are associated with the same physical core). A processor stalls when it must wait for data it has requested, in order to finish processing the present thread. The degree of benefit seen when using a hyper-threaded, or multi-core, processor depends on the needs of the software, and how well it and the operating system are written to manage the processor efficiently.[8]

Hyper-threading works by duplicating certain sections of the processor—those that store the [architectural state](/source/Architectural_state)—but not duplicating the main [execution resources](/source/Execution_unit). This allows a hyper-threading processor to appear as the usual "physical" processor plus an extra "[logical](/source/Virtualization)" processor to the host operating system (HTT-unaware operating systems see two "physical" processors), allowing the operating system to schedule two threads or processes simultaneously and appropriately. When execution resources in a hyper-threaded processor are not in use by the current task, and especially when the processor is stalled, those execution resources can be used to execute another scheduled task. (The processor may stall due to a [cache miss](/source/CPU_cache#Cache_miss), [branch misprediction](/source/Branch_misprediction), or [data dependency](/source/Data_dependency).)[9]

This technology is transparent to operating systems and programs. The minimum that is required to take advantage of hyper-threading is [symmetric multiprocessing](/source/Symmetric_multiprocessing) (SMP) support in the operating system, since the logical processors appear no different to the operating system than physical processors.

It is possible to optimize operating system behavior on multi-processor, hyper-threading capable systems. For example, consider an SMP system with two physical processors that are both hyper-threaded (for a total of four logical processors). If the operating system's thread [scheduler](/source/Scheduling_(computing)) is unaware of hyper-threading, it will treat all four logical processors the same. If only two threads are eligible to run, it might choose to schedule those threads on the two logical processors that happen to belong to the same physical processor. That processor would be extremely busy, and would share execution resources, while the other processor would remain idle, leading to poorer performance than if the threads were scheduled on different physical processors. This problem can be avoided by improving the scheduler to treat logical processors differently from physical processors, which is, in a sense, a limited form of the scheduler changes required for [NUMA](/source/Non-Uniform_Memory_Access) systems.

## History

The first published paper describing what is now known as hyper-threading in a general purpose computer was written by Edward S. Davidson and Leonard. E. Shar in 1973.[10]

[Denelcor, Inc.](https://en.wikipedia.org/w/index.php?title=Denelcor,_Inc.&action=edit&redlink=1) introduced [multi-threading](/source/Multithreading_(computer_architecture)) with the [Heterogeneous Element Processor](/source/Heterogeneous_Element_Processor) (HEP) in 1982. The HEP pipeline could not hold multiple instructions from the same process. Only one instruction from a given process was allowed to be present in the pipeline at any point in time. Should an instruction from a given process block the pipe, instructions from other processes would continue after the pipeline drained.

The US patent for the technology behind hyper-threading was granted to Kenneth Okin at [Sun Microsystems](/source/Sun_Microsystems) in November 1994. At that time, [CMOS](/source/CMOS) process technology was not advanced enough to allow for a cost-effective implementation.[11]

Intel implemented hyper-threading on an x86 architecture processor in 2002 with the Foster MP-based [Xeon](/source/Xeon). It was also included on the 3.06 GHz Northwood-based Pentium 4 in the same year, and then remained as a feature in every Pentium 4 HT, Pentium 4 Extreme Edition and Pentium Extreme Edition processor since. The Intel Core & Core 2 processor lines (2006) that succeeded the Pentium 4 model line didn't utilize hyper-threading. The processors based on the [Core microarchitecture](/source/Intel_Core_(microarchitecture)) did not have hyper-threading because the Core microarchitecture was a descendant of the older [P6 microarchitecture](/source/P6_(microarchitecture)). The P6 microarchitecture was used in earlier iterations of Pentium processors, namely, the [Pentium Pro](/source/Pentium_Pro), [Pentium II](/source/Pentium_II) and [Pentium III](/source/Pentium_III) (plus their [Celeron](/source/Celeron) & [Xeon](/source/Xeon) derivatives at the time). [Windows 2000](/source/Windows_2000) SP3 and [Windows XP SP1](/source/Windows_XP_SP1) have added support for hyper-threading.

Intel released the [Nehalem microarchitecture](/source/Nehalem_(microarchitecture)) (Core i7) in November 2008, in which hyper-threading made a return. The first generation Nehalem processors contained four physical cores and effectively scaled to eight threads. Since then, both two- and six-core models have been released, scaling four and twelve threads respectively.[12] Earlier [Intel Atom](/source/Intel_Atom) cores were in-order processors, sometimes with hyper-threading ability, for low power mobile PCs and low-price desktop PCs.[13] The [Itanium](/source/Itanium) 9300 launched with eight threads per processor (two threads per core) through enhanced hyper-threading technology. The next model, the Itanium 9500 (Poulson), features a 12-wide issue architecture, with eight CPU cores with support for eight more virtual cores via hyper-threading.[14] The Intel Xeon 5500 server chips also utilize two-way hyper-threading.[15][16]

## Performance claims

According to Intel, the first hyper-threading implementation used only 5% more [die area](/source/Die_(integrated_circuit)) than the comparable non-hyperthreaded processor, but the performance was 15–30% better.[17][18] Intel claims up to a 30% performance improvement compared with an otherwise identical, non-simultaneous multithreading Pentium 4. [Tom's Hardware](/source/Tom's_Hardware) states: "In some cases a P4 running at 3.0 GHz with HT on can even beat a P4 running at 3.6 GHz with HT turned off."[19] Intel also claims significant performance improvements with a hyper-threading-enabled Pentium 4 processor in some artificial-intelligence algorithms.

Overall the performance history of hyper-threading was a mixed one in the beginning. As one commentary on high-performance computing from November 2002 notes:[20]

Hyper-Threading can improve the performance of some [MPI](/source/Message_Passing_Interface) applications, but not all. Depending on the cluster configuration and, most importantly, the nature of the application running on the cluster, performance gains can vary or even be negative. The next step is to use performance tools to understand what areas contribute to performance gains and what areas contribute to performance degradation.

As a result, performance improvements are very application-dependent;[21] however, when running two programs that require full attention of the processor, it can actually seem like one or both of the programs slows down slightly when Hyper-Threading Technology is turned on.[22] This is due to the [replay system](/source/Replay_system) of the Pentium 4 tying up valuable execution resources, equalizing the processor resources between the two programs, which adds a varying amount of execution time. The Pentium 4 "Prescott" and the Xeon "Nocona" processors received a replay queue that reduces execution time needed for the replay system and completely overcomes the performance penalty.[23]

According to a November 2009 analysis by Intel, performance impacts of hyper-threading result in increased overall latency in case the execution of threads does not result in significant overall throughput gains, which vary[21] by the application. In other words, overall processing latency is significantly increased due to hyper-threading, with the negative effects becoming smaller as there are more simultaneous threads that can effectively use the additional hardware resource utilization provided by hyper-threading.[24] A similar performance analysis is available for the effects of hyper-threading when used to handle tasks related to managing network traffic, such as for processing [interrupt requests](/source/Interrupt_request_(PC_architecture)) generated by [network interface controllers](/source/Network_interface_controller) (NICs).[25] Another paper claims no performance improvements when hyper-threading is used for interrupt handling.[26]

## Drawbacks

When the first HT processors were released, many operating systems were not optimized for hyper-threading technology (e.g. Windows 2000 and Linux older than 2.4).[27]

In 2006, hyper-threading was criticised for energy inefficiency.[28] For example, [ARM](/source/ARM_Holdings) (a specialized, low-power, CPU design company), stated that simultaneous multithreading can use up to 46% more power than ordinary dual-core designs. Furthermore, they claimed that SMT increases [cache thrashing](/source/Cache_thrashing) by 42%, whereas [dual core](/source/Dual_core) results in a 37% decrease.[29]

In 2010, ARM said it might include simultaneous multithreading in its future chips;[30] however, this was rejected in favor of their 2012 64-bit design.[31] ARM produced SMT cores in 2018.[32]

In 2013, Intel dropped SMT in favor of [out-of-order execution](/source/Out-of-order_execution) for its [Silvermont](/source/Silvermont) processor cores, as they found this gave better performance with better power efficiency than a lower number of cores with SMT.[33]

In 2017, it was revealed that Intel's [Skylake](/source/Skylake_(microarchitecture)) and [Kaby Lake](/source/Kaby_Lake) processors had a bug in their implementation of hyper-threading that could cause data loss.[34] [Microcode](/source/Microcode) updates were later released to address the issue.[35][36][37]

In 2019, with [Coffee Lake](/source/Coffee_Lake), Intel temporarily moved away from including hyper-threading in mainstream Core i7 desktop processors except for highest-end Core i9 parts or Pentium Gold CPUs.[38] It also began to recommend disabling hyper-threading, as [new CPU vulnerability](/source/Spectre_(security_vulnerability)) attacks were revealed which could be mitigated by disabling HT.[39]

## Security

In May 2005, [Colin Percival](/source/Colin_Percival) demonstrated that a malicious thread on a Pentium 4 can use a timing-based [side-channel attack](/source/Side-channel_attack) to monitor the [memory access patterns](/source/Memory_access_pattern) of another thread with which it shares a cache, allowing the theft of cryptographic information. This is not actually a [timing attack](/source/Timing_attack), as the malicious thread measures the time of only its own execution. Potential solutions to this include the processor changing its cache eviction strategy or the operating system preventing the simultaneous execution, on the same physical core, of threads with different privileges.[40] In 2018 the [OpenBSD](/source/OpenBSD) operating system disabled hyper-threading "in order to avoid data potentially leaking from applications to other software" caused by the [Foreshadow/L1TF](/source/Foreshadow_(security_vulnerability)) vulnerabilities.[41][42] In 2019 a [set of vulnerabilities](/source/Microarchitectural_Data_Sampling) led to security experts recommending the disabling of hyper-threading on all devices.[43]

## See also

- [Barrel processor](/source/Barrel_processor)

- [Computer multitasking](/source/Computer_multitasking)

- [Multi-core processor](/source/Multi-core_processor)

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## External links

- [Intel Demonstrates Breakthrough Processor Design](http://www.intel.com/pressroom/archive/releases/2001/20010828comp.htm), a press release from August 2001

- [Intel – high level overview of Hyper-threading](http://www.intel.com/technology/platform-technology/hyper-threading/)

- [Hyper-threading on MSDN Magazine](http://msdn.microsoft.com/en-us/magazine/cc300701.aspx)

- [introductory article](https://arstechnica.com/articles/paedia/cpu/hyperthreading.ars) from Ars Technica

- [US Patent Number 4,847,755](http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=4,847,755.PN.&OS=PN/4,847,755&RS=PN/4,847,755)

- [Merom, Conroe, Woodcrest lose HyperThreading](https://www.theregister.co.uk/2005/08/23/intel_next_gen_architecture/)

- [ZDnet: Hyperthreading hurts server performance, say developers](https://www.zdnet.com/article/hyperthreading-hurts-server-performance-say-developers/)

- [ARM is no fan of HyperThreading](https://web.archive.org/web/20090906005322/http://www.theinquirer.net/inquirer/news/1037948/arm-fan-hyperthreading) - Outlines problems of SMT solutions

- [The Impact of Hyper-Threading on Processor Resource Utilization in Production Applications](https://www.nas.nasa.gov/assets/pdf/papers/saini_s_impact_hyper_threading_2011.pdf)

v t e Processor technologies Models Abstract machine Stored-program computer Finite-state machine with datapath Hierarchical Deterministic finite automaton Queue automaton Cellular automaton Quantum cellular automaton Turing machine Alternating Turing machine Universal Post–Turing Quantum Nondeterministic Turing machine Probabilistic Turing machine Hypercomputation Zeno machine Belt machine Stack machine Register machines Counter Pointer Random-access Random-access stored program Architecture Microarchitecture Von Neumann Harvard modified Dataflow Transport-triggered Cellular Endianness Memory access NUMA HUMA Load–store Register/memory Cache hierarchy Memory hierarchy Virtual memory Secondary storage Heterogeneous Fabric Multiprocessing Cognitive Neuromorphic Instruction set architectures Types Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes Instruction sets Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others Execution Instruction pipelining Pipeline stall Operand forwarding Classic RISC pipeline Hazards Data dependency Structural Control False sharing Out-of-order Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue Speculative Branch prediction Memory dependence prediction Parallelism Level Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed Multithreading Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD Processor performance Transistor count Instructions per cycle (IPC) Cycles per instruction (CPI) Instructions per second (IPS) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic updates per second (SUPS) Performance per watt (PPW) Cache performance metrics Computer performance by orders of magnitude Types Central processing unit (CPU) Graphics processing unit (GPU) GPGPU Vector Barrel Stream Tile processor Coprocessor PAL ASIC FPGA FPOA CPLD Multi-chip module (MCM) System in a package (SiP) Package on a package (PoP) By application Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor Systems on chip System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC) Hardware accelerators Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor Word size 1-bit 4-bit 8-bit 12-bit 15-bit 16-bit 24-bit 32-bit 48-bit 64-bit 128-bit 256-bit 512-bit bit slicing others variable Core count Single-core Multi-core Manycore Heterogeneous architecture Components Core Cache CPU cache Scratchpad memory Data cache Instruction cache replacement policies coherence Bus Clock rate Clock signal FIFO Functional units Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder Logic Combinational Sequential Glue Logic gate Quantum Array Registers Processor register Status register Stack register Register file Memory buffer Memory address register Program counter Control unit Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter Datapath Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter Circuitry Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch Power management PMU APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating Performance per watt (PPW) Related History of general-purpose CPUs Microprocessor chronology Processor design Digital electronics Hardware security module Semiconductor device fabrication Tick–tock model Pin grid array Chip carrier

v t e Intel technology Platforms Centrino Centrino 2 Viiv MID Tablet CULV Ultrabook Skulltrail NUC Galileo Edison Curie Evo Discontinued Common Building Block MultiProcessor Specification Intel Communication Streaming Architecture Intel Inboard 386 Intel Play Mobile Module Connector MMC-1 MMC-2 Current Advanced Programmable Interrupt Controller CNVi Intel Turbo Boost vPro Intel Secure Key Intel Management Engine Active Management Technology AMT versions High-bandwidth Digital Content Protection High Definition Audio Hub Architecture Rapid Storage Technology SpeedStep Serial Digital Video Out Host Embedded Controller Interface Hyper-threading Omni-Path Platform Environment Control Interface QuickPath Interconnect Platform Controller Hub System Management Bus Thunderbolt Ultra Path Interconnect Upcoming Silicon Photonics Link

v t e Parallel computing General Distributed computing Parallel computing Parallel algorithm Massively parallel Cloud computing High-performance computing Multiprocessing Manycore processor GPGPU Computer network Systolic array Levels Bit Instruction Thread Task Data Memory Loop Pipeline Multithreading Temporal Simultaneous (SMT) Simultaneous and heterogenous Speculative (SpMT) Preemptive Cooperative Clustered multi-thread (CMT) Hardware scout Theory PRAM model PEM model Analysis of parallel algorithms Amdahl's law Gustafson's law Cost efficiency Karp–Flatt metric Slowdown Speedup Elements Process Thread Fiber Instruction window Array Coordination Multiprocessing Memory coherence Cache coherence Cache invalidation Barrier Synchronization Application checkpointing Programming Stream processing Dataflow programming Models Implicit parallelism Explicit parallelism Concurrency Non-blocking algorithm Hardware Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing MISD MIMD Dataflow architecture Pipelined processor Superscalar processor Vector processor Multiprocessor symmetric asymmetric Memory shared distributed distributed shared UMA NUMA COMA Massively parallel computer Computer cluster Beowulf cluster Grid computer Hardware acceleration APIs Ateji PX Boost Chapel HPX Charm++ Cilk Coarray Fortran CUDA Dryad C++ AMP Global Arrays GPUOpen MPI OpenMP OpenCL OpenHMPP OpenACC Parallel Extensions PVM pthreads RaftLib ROCm UPC TBB ZPL Problems Automatic parallelization Cache stampede Deadlock Deterministic algorithm Embarrassingly parallel Parallel slowdown Race condition Software lockout Scalability Starvation Category: Parallel computing

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Adapted from the Wikipedia article [Hyper-threading](https://en.wikipedia.org/wiki/Hyper-threading) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Hyper-threading?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.