# Datapath

> Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Datapath
> Markdown URL: https://mediated.wiki/source/Datapath.md
> Source: https://en.wikipedia.org/wiki/Datapath
> Source revision: 1333945958
> License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/)

{{Short description|CPU's internal components except the control unit}}
A '''data path''' is a collection of [functional unit](/source/functional_unit)s  such as [arithmetic logic unit](/source/arithmetic_logic_unit)s (ALUs) or [multiplier](/source/Binary_multiplier)s that perform data processing operations, [register](/source/Processor_register)s, and [buses](/source/Bus_(computing)).{{r|NullLobur2006}} Along with the [control unit](/source/control_unit) it composes the [central processing unit](/source/central_processing_unit) (CPU).{{r|NullLobur2006}} A larger data path can be made by joining multiple data paths using [multiplexers](/source/multiplexers).

A '''data path''' is the ALU, the set of registers, and the CPU's internal bus(es) that allow data to flow between them.<ref>
Edward Bosworth.
[http://www.edwardbosworth.com/My5155_Slides/Chapter09/ComputerArchitectureOverview.htm "Overview of Computer Architecture"].
</ref>

thumb|upright=2|A microarchitecture data path organized around a single bus
The simplest design for a CPU uses one common internal bus.
Efficient addition requires a slightly more complicated three-internal-bus structure.<ref>
Edward Bosworth.
[http://www.edwardbosworth.com/My5155_Slides/Chapter11/CPUBusStructure.htm "CPU Bus Structure"].
</ref>
Many relatively simple CPUs have a 2-read, 1-write [register file](/source/register_file)
connected to the 2 inputs and 1 output of the ALU.

During the late 1990s, there was growing research in the area of [reconfigurable](/source/Reconfigurable_computing) data paths—data paths that may be re-purposed at run-time using [programmable fabric](/source/Field-programmable_gate_array)—as such designs may allow for more efficient processing as well as substantial power savings.<ref>J. R. Hauser and J. Wawrzynek, [http://class.ece.iastate.edu/tyagi/cpre583/documents/garp.pdf Garp: a MIPS processor with a reconfigurable coprocessor], FCCM’97, 1997, pp. 12–21. {{Webarchive|url=https://web.archive.org/web/20170922233250/http://class.ece.iastate.edu/tyagi/cpre583/documents/garp.pdf |date=2017-09-22 }}</ref>

== Finite-state machine with data path ==

A '''finite-state machine with data path''' ('''FSMD''')  is a mathematical abstraction which combines a [finite-state machine](/source/finite-state_machine), which controls the [program flow](/source/program_flow), with a data path. It can be used to design [digital logic](/source/digital_logic) or [computer program](/source/computer_program)s.<ref>{{Cite book|last1=Zhu|first1=Jianwen|last2=Gajski|first2=Daniel D.|title=Proceedings of the seventh international workshop on Hardware/Software codesign - CODES '99 |chapter=A unified formal model of ISA and FSMD |date=1999-03-01|location=New York, NY, USA|publisher=Association for Computing Machinery|pages=121–125|doi=10.1145/301177.301504|isbn=978-1-58113-132-1|s2cid=5426988 |doi-access=free}}</ref><ref>{{Cite book|last1=Hsu|first1=Y.C.|last2=Liu|first2=T.Y.|last3=Tsai|first3=F.S.|last4=Lin|first4=S.Z.|last5=Yu|first5=C.|title=Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems |chapter=Digital design from concept to prototype in hours |date=1994-12-05|chapter-url=https://ieeexplore.ieee.org/document/514545/;jsessionid=MYQQA-0VMOI3jrTe_LSwPUmf2Be40nidbIiIztKGURh20Ig67Xk2!-1937166891|pages=175–181|doi=10.1109/APCCAS.1994.514545|isbn=0-7803-2440-4 |s2cid=61056791 }}</ref>

FSMDs are essentially sequential programs in which statements have been scheduled into states, thus resulting in more complex state diagrams. Here, a program is converted into a complex state diagram in which states and arcs may include [arithmetic expression](/source/arithmetic_expression)s, and those expressions may use external inputs and outputs as well as variables. The FSMD level of abstraction is often referred to as the [register-transfer level](/source/register-transfer_level).

FSMs do not use variables or arithmetic operations/conditions, thus FSMDs are more powerful than FSMs. An FSMD is equivalent to a [Turing machine](/source/Turing_machine) in expressiveness.

== References ==
<references>
<ref name=NullLobur2006>{{cite book
|first1 = Linda
|last1 = Null
|first2 = Julia
|last2 = Lobur
|title = The Essentials of Computer Organization and Architecture
|url=https://books.google.com/books?id=QGPHAl9GE-IC
|year=2006
|publisher=Jones & Bartlett Learning
|page = 2016
|quote = All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units... connected by buses... where the timing is controlled by clocks.
|isbn=978-0-7637-3769-6}}</ref>
</references>

Category:Central processing unit
Category:Digital electronics
{{CPU technologies}}

---
Adapted from the Wikipedia article [Datapath](https://en.wikipedia.org/wiki/Datapath) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Datapath?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.