# Coreboot > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Coreboot > Markdown URL: https://mediated.wiki/source/Coreboot.md > Source: https://en.wikipedia.org/wiki/Coreboot > Source revision: 1351424037 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) {{Short description|Open-source computer firmware}} {{Use dmy dates|date=July 2019}} {{Lowercase title}} {{Infobox software | name = coreboot | logo = Coreboot full.svg{{!}}class=skin-invert | logo alt = Graphic of a running hare in black and white above text "coreboot" in lowercase sans-serif font | logo size = 150px | screenshot = | caption = | author = Ronald G. Minnich, Eric Biederman, Li-Ta (Ollie) Lo, Stefan Reinauer, and the coreboot community | developer = | released = {{Start date and age|df=yes|1999}} | latest release version = {{Wikidata|properties|references|edit|P348|P548=Q2804309}} | latest release date = {{Start date and age|{{Wikidata|qualifier|single|P348|P548=Q2804309|P577}}}}{{Cite web |url=https://www.coreboot.org/releases |title=Releases |date=n.d. |website=coreboot}} | programming language = Mostly [C](/source/C_(programming_language)), about 1% in [assembly](/source/Assembly_language) and optionally [SPARK](/source/SPARK_(programming_language)) | platform = [IA-32](/source/IA-32), [x86-64](/source/x86-64), [ARMv7](/source/ARMv7),{{cite web|url=https://www.coreboot.org/ARM |title=ARM |publisher=coreboot |date=15 October 2013 |access-date=1 February 2014}} ARMv8, [RISC-V](/source/RISC-V), POWER8 | genre = [Firmware](/source/Firmware) | license = [GPLv2](/source/GPLv2)-only{{Cite web|url=https://github.com/coreboot/coreboot/blob/master/COPYING|title=coreboot's licence|date=1991|website=github.com|access-date=2018-10-13}} }} '''coreboot''' (formerly '''LinuxBIOS'''){{cite mailing list |date=12 January 2008 |title=[LinuxBIOS] Welcome to coreboot |author=Ron Minnich |mailing-list=LinuxBIOS |url=http://coreboot.org/pipermail/coreboot/2008-January/029135.html |url-status=dead |archive-url=https://web.archive.org/web/20130601003256/https://coreboot.org/pipermail/coreboot/2008-January/029135.html |archive-date=June 1, 2013 |access-date=January 12, 2008}} is a [free and open‑source](/source/Free_and_open-source_software) project that provides lightweight [firmware](/source/firmware) to initialize [hardware](/source/Computer_hardware) and then load an [operating system](/source/operating_system). It is designed to replace [proprietary](/source/Proprietary_software) firmware (traditional [BIOS](/source/BIOS) or [UEFI](/source/UEFI) implementations) by performing the minimal tasks required to start a modern [32-bit](/source/32-bit) or [64-bit](/source/64-bit) [operating system](/source/operating_system). Because coreboot performs low‑level hardware initialization, it must be ported to each supported [chipset](/source/chipset) and [motherboard](/source/motherboard) model; consequently, availability is limited to platforms for which support has been implemented. One of the well‑known variants of coreboot is [Libreboot](/source/Libreboot), a [software distribution](/source/software_distribution) that focuses on removing proprietary [binary blob](/source/binary_blob)s from the firmware stack. == History == The coreboot project began with the goal of creating a BIOS that boots quickly and handles errors intelligently.{{cite web |author=Anton Borisov |url=http://www.h-online.com/open/features/The-Open-Source-BIOS-is-Ten-An-interview-with-the-coreboot-developers-746525.html?view=print |title=The Open Source BIOS is Ten. An interview with the coreboot developers |website=[The H](/source/The_H) |date=2009 |archive-url=https://web.archive.org/web/20120916212555/http://www.h-online.com/open/features/The-Open-Source-BIOS-is-Ten-An-interview-with-the-coreboot-developers-746525.html?view=print |archive-date=16 September 2012 |url-status=dead}}' It is distributed under the terms of the [GNU General Public License](/source/GNU_General_Public_License) version 2 (GPLv2). Main contributors include [LANL](/source/Los_Alamos_National_Laboratory), [SiS](/source/Silicon_Integrated_Systems), [AMD](/source/Advanced_Micro_Devices), Coresystems and Linux Networx, Inc, as well as motherboard vendors [MSI](/source/Micro-Star_International), [Gigabyte](/source/Gigabyte_Technology) and [Tyan](/source/Tyan), which offer coreboot alongside their standard BIOS or provide specifications of the hardware interfaces for some of their motherboards. [Google](/source/Google) partly sponsors the coreboot project.{{Cite web|url=http://google-code-updates.blogspot.com/2006/11/google-sponsors-linuxbios-project.html|title=Google Sponsors the LinuxBIOS project|access-date=29 September 2023|archive-date=6 February 2012|archive-url=https://web.archive.org/web/20120206205540/http://google-code-updates.blogspot.com/2006/11/google-sponsors-linuxbios-project.html|url-status=bot: unknown}} [CME Group](/source/CME_Group), a financial public company, began supporting the coreboot project in 2009.{{cite web|url=http://www.wallstreetandtech.com/it-infrastructure/showArticle.jhtml?articleID=217400294|title=CME Group Dives Into Coreboot and Other Linux Open Source Projects|work=Wall Street & Technology|access-date=23 September 2015|archive-url=https://web.archive.org/web/20100812092429/http://www.wallstreetandtech.com/it-infrastructure/showArticle.jhtml?articleID=217400294|archive-date=12 August 2010|url-status=dead}} Other than the first three models, all [Chromebook](/source/Chromebook)s run coreboot.{{cite web |url=http://www.coreboot.org/Chromebooks |title=Chromebooks |publisher=coreboot |date=16 January 2014 |access-date=17 February 2014 |archive-url=https://web.archive.org/web/20160508225442/https://www.coreboot.org/Chromebooks |archive-date=8 May 2016 |url-status=dead }} Code from [Das U-Boot](/source/Das_U-Boot) has been assimilated to enable support for processors based on the [ARM instruction set](/source/ARM_architecture).{{cite web|url=http://blogs.coreboot.org/blog/2011/06/05/gsoc2011week-1-analysis-of-u-boot-arm-boot-code/ |title=GSoC2011(Week 1): Analysis of U-boot ARM boot code | coreboot developer blogs|date=5 June 2011 |access-date=12 April 2014}} In June 2019, coreboot began to use the [NSA](/source/NSA) software [Ghidra](/source/Ghidra) for its [reverse engineering](/source/reverse_engineering) efforts on [firmware-specific](/source/Firmware) problems following the release of the suite as [free and open source software](/source/free_and_open_source_software).{{Cite web |title=Coreboot nutzt NSA-Tool zum Reverse Engineering |url=https://www.golem.de/news/ghidra-coreboot-nutzt-nsa-tool-zum-reverse-engineering-1906-141746.html |access-date=2023-05-04 |website=[Golem.de](/source/Golem.de)}} == Supported platforms == coreboot supports multiple CPU architectures, including [IA-32](/source/IA-32), [x86-64](/source/x86-64), [ARM](/source/ARM_architecture_family), [ARM64](/source/AArch64), [MIPS](/source/MIPS_architecture) and [RISC-V](/source/RISC-V). Support covers a variety of [system-on-a-chip](/source/system-on-a-chip) (SoC) platforms as well; early development focused on AMD [Geode](/source/Geode_(processor)) processors (notably those used in the [OLPC](/source/One_Laptop_per_Child) project). Artec Group added Geode LX support for its [ThinCan](/source/ThinCan) model DBE61; that code was adopted by AMD and further improved for the OLPC after it was upgraded to the Geode LX platform, and is further developed by the coreboot community to support other Geode variants. coreboot can be flashed onto a Geode platform using [Flashrom](/source/Flashrom_(utility)). From that initial development on AMD Geode based platforms, coreboot support has been extended onto many AMD processors and chipsets. The processor list includes Family 0Fh and 10h ([K8](/source/AMD_K8) core), and recently Family 14h ([Bobcat](/source/Bobcat_(microarchitecture)) core, [Fusion APU](/source/AMD_APU)). coreboot support also extends to AMD chipsets: [RS690](/source/AMD_690_chipset_series), [RS7xx](/source/AMD_700_chipset_series), [SB600](/source/AMD_580_chipset_series), and SB8xx. In AMD Generic Encapsulated Software Architecture ([AGESA](/source/AGESA)){{mdashb}}a [bootstrap](/source/Bootstrapping) protocol by which system devices on AMD64 mainboards are initialized{{mdashb}}was open sourced in early 2011, aiming to provide required functionality for coreboot system initialization on AMD64 hardware.{{cite web | title = Technical details on AMD's coreboot source code release | url = http://community.amd.com/community/amd-blogs/business/embedded-systems/blog/2011/02/28/technical-details-on-amd-s-coreboot-source-code-release |publisher =[AMD](/source/Advanced_Micro_Devices) |date=28 February 2011 | archive-url=https://web.archive.org/web/20140325040416/http://community.amd.com/community/amd-blogs/amd-business/blog/2011/02/28/technical-details-on-amd-s-coreboot-source-code-release | archive-date=25 March 2014 | access-date=1 February 2016 | url-status=dead }} However, as of 2014 such releases never became the basis for future development by AMD, and were subsequently halted.{{cite web|url=https://mail.coreboot.org/pipermail/coreboot/2014-November/078892.html |title=AMD's binary-only AGESA libraries | first=Bruce |last=Griffith |date=2014-11-05 |access-date=2017-05-08 }} Devices that could be preloaded with coreboot or one of its derivatives include: ;[Lenovo](/source/Lenovo)/[IBM](/source/IBM):The Libreboot T400 and X200 (rebranded ThinkPad T400 and X200, respectively, available from Minifree, previously known as Gluglug).{{cite web |title=Minifree |url=http://minifree.org/ |archive-date=25 September 2015 |access-date=24 September 2015 |website=Ministry of Freedom - Products|archive-url=https://web.archive.org/web/20150925120409/http://minifree.org/ }}{{cite web|url=https://www.fsf.org/resources/hw/endorsement/gluglug|title=The Gluglug|work=fsf.org|access-date=23 September 2015|archive-url=https://web.archive.org/web/20150923124716/https://www.fsf.org/resources/hw/endorsement/gluglug|archive-date=23 September 2015|url-status=dead}} ;Artec Group: [ThinCan](/source/ThinCan) models DBE61, DBE62 and DBE63, and fanless server/router hardware manufactured by [PC Engines](/source/PC_Engines).{{cite web|url=https://github.com/pcengines/coreboot|title=pcengines/coreboot|website=[GitHub](/source/GitHub) |access-date=16 September 2019}} ; [Purism](/source/Purism_(company)): [Librem](/source/Librem) laptops come with coreboot.{{cite web |title=coreboot Firmware on Purism Librem devices |url=https://puri.sm/coreboot/ |access-date=19 June 2020}}{{cite web |title=Purism Laptops To Use 'Heads' Firmware To Protect Against Rootkits, Tampering (Updated) |date=27 February 2018 |url=https://www.tomshardware.com/news/purism-heads-rootkit-tampering-protection,34128.html |access-date=19 June 2020}} ;Others :Some [System76](/source/System76) PCs use coreboot TianoCore firmware, including open source [Embedded Controller](/source/Embedded_Controller) firmware. :Dasharo offers an alternative coreboot-based firmware distribution for computers from [MSI](/source/Micro-Star_International), [NovaCustom](/source/NovaCustom) and [Nitrokey](/source/Nitrokey), among others.{{cite web |title=New Dasharo v1.1 Firmware For The MSI Z690 Board - Phoronix |date=22 November 2022 |url=https://www.phoronix.com/news/Dasharo-1.1-MSI-Z690-Board |access-date=27 October 2023}}{{cite web |title=NovaCustom-Dasharo October-2023 Firmware Update (ADL v1.7.0 & TGL v1.5.0) - NovaCustom|date=19 September 2023 |url=https://configurelaptop.eu/novacustom-dasharo-october-2023-firmware-update-adl-v1-7-0-tgl-v1-5-0/ |access-date=27 October 2023}}{{cite web |title= The NitroPC Pro is Qubes-Certified! - Nitrokey |date=24 September 2023 |url=https://www.nitrokey.com/news/2023/nitropc-pro-qubes-certified |access-date=27 October 2023}} :StarLabs Systems use coreboot firmware, as an alternative.[https://fossbytes.com/starbook-mk-v-from-star-labs-review/ Starbook mk v review] - fossbytes :Some [Tesla Model 3](/source/Tesla_Model_3) cars have adopted [Ryzen Embedded](/source/Ryzen_Embedded) or [Intel Atom](/source/Intel_Atom) processor on the car computer, and adopted coreboot as the bootloader.{{citation needed|date=February 2025}} == Design == Coreboot typically loads a [Linux kernel](/source/Linux_kernel), but it can load any other [stand-alone](/source/standalone_program) [ELF](/source/Executable_and_Linkable_Format) executable, such as [iPXE](/source/iPXE), [gPXE](/source/gPXE) or Etherboot that can boot a Linux kernel [over a network](/source/Network_booting), or [SeaBIOS](/source/SeaBIOS)[http://www.coreboot.org/SeaBIOS SeaBIOS] (previously known as LegacyBIOS) is an open-source legacy BIOS implementation that can load a Linux kernel, [Windows 2000](/source/Windows_2000) and later, and BSDs; Windows 2000/[XP](/source/Windows_XP) and [OpenBSD](/source/OpenBSD) support was previously provided by ADLO.{{Cite web|url=http://www.coreboot.org/ADLO|archiveurl=https://web.archive.org/web/20101125130605/http://www.coreboot.org/ADLO|url-status=dead|title=coreboot Add-on Layer (ADLO)|archivedate=25 November 2010}}{{cite web |url=http://www.missl.cs.umd.edu/sebos_phase2.html |title=SEBOS, Security Enhanced Bootloader for Operating Systems, Phase 2 |archive-url=https://web.archive.org/web/20070619101948/http://www.missl.cs.umd.edu/sebos_phase2.html |archive-date=19 June 2007 |url-status=dead}} - adding PC BIOS Services to coreboot via Bochs BIOS coreboot can also load a [kernel](/source/Kernel_(operating_system)) from any supported device, such as Myrinet, Quadrics, or SCI [cluster](/source/Computer_cluster) interconnects. Booting other kernels directly is also possible, such as a [Plan 9](/source/Plan_9_from_Bell_Labs) kernel. Instead of loading a kernel directly, coreboot can pass control to a dedicated boot loader, such as a coreboot-capable version of [GNU GRUB](/source/GNU_GRUB) 2. Coreboot is primarily implemented in [C](/source/C_(programming_language)), with a small amount of [assembly code](/source/assembly_code). Choosing C as the primary programming language facilitates [code audit](/source/code_audit)s when compared to contemporary PC BIOS that was generally written in assembly,{{cite web |url=https://phoenixts.com/blog/uefi-vs-legacy-bios/ |title=Comparison of UEFI and legacy BIOS}} pronouncing that same advantage for UEFI which results in improved security. There is build and runtime support to write parts of coreboot in [Ada](/source/Ada_(programming_language)){{cite web |url=https://review.coreboot.org/cgit/coreboot.git/commit/src/lib/gnat?id=e0ed9025cf7453212e5e5a845e34e0b7ecfa3eb9 |title=commit}} adding that support to further raise the security bar, but it is currently only sporadically used. The source code is released under the [GNU GPL version 2](/source/GPL_version_2) license. Coreboot performs the absolute minimal amount of hardware initialization and then passes control to the [operating system](/source/operating_system). As a result, there is no coreboot code running once the operating system has taken control. A feature of coreboot is that the [x86](/source/x86) version runs in [32-bit](/source/32-bit) mode after executing only ten instructions{{Cite web |url=http://lxr.linux.no/coreboot-v3+r777/arch/x86/geodelx/stage0.S |title=coreboot v3 early startup code |access-date=17 August 2008 |archive-url=https://archive.today/20120710041412/http://lxr.linux.no/coreboot-v3+r777/arch/x86/geodelx/stage0.S |archive-date=10 July 2012 |url-status=dead }} (almost all other x86 BIOSes run exclusively in [16-bit](/source/16-bit) mode). This is similar to the modern [UEFI](/source/UEFI) firmware, which is used on newer PC hardware. === Initializing DRAM === The most difficult hardware that coreboot initializes is the [DRAM controller](/source/Memory_controller)s and [DRAM](/source/Dynamic_random-access_memory). In some cases, technical documentation on this subject is [NDA](/source/Non-disclosure_agreement) restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's [general purpose registers](/source/Processor_register) or Cache-as-RAM as temporary storage. romcc, a [C](/source/C_(programming_language)) [compiler](/source/compiler) that uses registers instead of RAM, eases the task. Using romcc, it is relatively easy to make [SMBus](/source/System_Management_Bus) accesses to the [SPD](/source/Serial_presence_detect) ROMs of the DRAM [DIMM](/source/DIMM)s, that allows the RAM to be used. With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM{{cite web |url=http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf |title=CAR: Using Cache as RAM in Linux BIOS |date=15 January 2009 |access-date=25 February 2014 |author1=Yinghai Lu |author2=Li-Ta Lo |author3=Gregory R. Watson |author4=Ronald G. Minnich |publisher=qmqm.pl |archive-url=https://web.archive.org/web/20160303223305/http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf |archive-date=3 March 2016 |url-status=dead }}{{Cite web|url=https://docs.huihoo.com/coreboot/LBCar.pdf|title=A Framework for Using Processor Cache as RAM (CAR)}} mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard. For most modern x86 platforms, closed source binary-only components provided by the vendor are used for DRAM setup. For Intel systems, FSP-M is required, while AMD has no current support. Binary AGESA is currently used for proprietary UEFI firmware on AMD systems, and this model is expected to carry over to any future AMD-related coreboot support.{{cite web|url=https://mail.coreboot.org/pipermail/coreboot/2014-November/078892.html|title=[coreboot] AMD's binary-only AGESA libraries|last=Griffith|first=Bruce|date=5 November 2014|access-date=2019-09-08}} == Developing and debugging coreboot == thumb|Hacking coreboot at Denver 2008 summit. Developers use a variety of hardware and software debugging tools when working on coreboot. These include in‑circuit [emulator](/source/emulator)s, [JTAG](/source/JTAG) probes (for example the Sage SmartProbe), and BIOS/firmware emulators. Code may be tested on emulators or downloaded to target hardware rather than being immediately flashed to a BIOS device.{{Cite web|url=http://www.se-eng.com/|archiveurl=https://web.archive.org/web/20110315080000/http://www.se-eng.com/|url-status=usurped|title=Sage Electronic Engineering - SmartProbe JTAG debugger, Sage EDK, coreboot and Embedded Systems and Software Engineering|archivedate=15 March 2011|website=www.se-eng.com}}{{cite web | url=http://www.loper-os.org/?p=1887 | title=Sage SmartProbe FAQ | publisher=S.Datskovskiy | access-date=30 April 2021}} being an example. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device. == Payloads == [[File:Coreboot+seaBIOS+on-x60.JPG|thumb|upright|[SeaBIOS](/source/SeaBIOS) payload running on a Lenovo [ThinkPad](/source/ThinkPad) X60]] coreboot loads a payload after hardware initialization. Payloads may be written with the {{Mono|libpayload}} helper library or be independent projects. Notable payloads include the following: * [SeaBIOS](/source/SeaBIOS) provides a "legacy BIOS" interface * [TianoCore EDK II](/source/TianoCore_EDK_II), the de-facto standard generic UEFI services implementation * [GRUB 2](/source/GNU_GRUB), most commonly used as an on-disk bootloader, can also be compiled as a coreboot payload * A [Linux](/source/Linux) kernel can also be used as payload, typically in the form of [LinuxBoot](/source/LinuxBoot) * Depthcharge is used by Google for [ChromeOS](/source/ChromeOS){{cite web | url = https://docs.google.com/presentation/d/1pH8ltQ3cGKy9dRaTxHtZbA50QLZCw6HE8LDoi1y_gcs/pub?start=false&loop=false&delayms=3000#slide=id.p | title = Depthcharge: The ChromeOS bootloader | access-date = 26 October 2015 | website = docs.google.com }} * A branch of [Das U-Boot](/source/Das_U-Boot) was used by Google for [ChromiumOS](/source/ChromiumOS) in the past{{cite web |url=https://groups.google.com/a/chromium.org/group/chromium-os-reviews/browse_thread/thread/8daf5b5ffe245c1d/0eda7e414407a923 |title=Modify u-boot code to allow building coreboot payload. [chromiumos/third_party/u-boot-next : chromeos-v2011.03] |date=24 July 2011 }} == {{Anchor|European Coreboot Conference|ECC}} European Coreboot Conference == One physical meeting is the European Coreboot Conference which was organized in October 2017 and lasted for three days. === Conference history === {| class="wikitable" style="font-size:90%;" ! Event and year !! Date !! Host city !! Venue !! Resources !! Themes |- | ECC2017 || 26.10. – 29.10 || [Bochum](/source/Bochum), Germany || [RUB](/source/Ruhr_University_Bochum) Convention Center || https://web.archive.org/web/20250218051639/https://ecc2017.com/ || |- |} == {{Anchor|LIBREBOOT}}Variants == coreboot has a number of variants from its original code base each with slightly different objectives:. * [Libreboot](/source/Libreboot) - A variant with a primary focus to remove some{{Cite web |date=2023-11-01 |title=Binary Blob Reduction Policy |url=https://libreboot.org/news/policy.html |access-date=2023-11-01 |archive-url=https://web.archive.org/web/20231101164256/https://libreboot.org/news/policy.html |archive-date=1 November 2023 }} binary blobs. * osboot - A variant similar to Libreboot that scrapped its only some blobs policy to increase hardware support and stability.{{Cite web |date=2021-03-15 |title=osboot project |url=https://osboot.org/ |access-date=2023-05-26 |archive-url=https://web.archive.org/web/20210315131008/https://osboot.org/ |archive-date=15 March 2021 }} Merged with libreboot as of November 2022.{{Cite web |date=2022-12-19 |title=Libreboot – Osboot is now part of Libreboot |url=https://libreboot.org/news/merge.html |access-date=2023-05-26 |archive-url=https://web.archive.org/web/20221219054437/https://libreboot.org/news/merge.html |archive-date=19 December 2022 }} * MrChromebox has developed a modified version of coreboot for ChromeOS based devices.{{Cite web |date=2022-04-17 |title=How to install ChromeOS Flex on a Chromebook |url=https://www.androidpolice.com/install-chromeos-flex-chromebook-explainer/ |access-date=2023-05-30 |website=Android Police |language=en}} * GNU Boot - A variant with a primary focus to remove all proprietary binary blobs.{{Cite web |date=2023-10-30 |title=GNU Boot Summary |url=https://savannah.gnu.org/projects/gnuboot |access-date=2023-10-30 |archive-url=https://web.archive.org/web/20231030210812/https://savannah.gnu.org/projects/gnuboot/ |archive-date=30 October 2023 }} * Canoeboot - A variant of Libreboot with a stricter policy, aiming again to remove all proprietary binary blobs.{{Cite web |date=16 November 2023 |title=Canoeboot project |url=https://canoeboot.org/ |access-date=16 November 2023 |archive-url=https://web.archive.org/web/20231116233556/https://canoeboot.org/ |archive-date=16 November 2023 }} * Dasharo - A distribution based on coreboot developed by 3mdeb, intended to simplify manufacturers shipping coreboot on products.{{Cite web | date=2024-01-29 | title=3mdeb Sp. z o.o. — Embedded Firmware development consultancy | url=https://3mdeb.com | access-date=2024-02-16 | archive-url=https://web.archive.org/web/20240216093245/https://3mdeb.com | archive-date=2024-02-16 }} They aim to make it easy for manufacturers to ship products with coreboot.{{Cite web | date=2023-10-22 | title=Dasharo • GitHub | url=https://github.com/Dasharo | access-date=2024-02-16 | archive-url=https://web.archive.org/web/20240216085150/https://github.com/Dasharo | archive-date=2024-02-16 }}{{Cite web | date=2024-02-09 | title=About Dasharo - Dasharo Universe | url=https://docs.dasharo.com | access-date=2024-02-16 | archive-url=https://web.archive.org/web/20240216090043/https://docs.dasharo.com/ | archive-date=2024-02-16 }} * Skulls - A variant aimed at ease of installation.{{Citation |last=Kepplinger-Novakovic |first=Martin |title=merge/skulls |date=2024-05-28 |url=https://github.com/merge/skulls |access-date=2024-05-29}} * Heads - A variant aimed at physical security and usage of free software, recommended for use with [QubesOS](/source/QubesOS).{{Cite web |title=About Heads |url=https://osresearch.net/ |access-date=2024-05-29 |website=Heads |language=en-US}}{{Citation |title=linuxboot/heads |date=2024-05-28 |url=https://github.com/linuxboot/heads |access-date=2024-05-29 |publisher=LinuxBoot}}{{Citation needed|date=July 2024|reason=The documentation and sources linked dont say that it is recommended for use with qubesOS}} * oreboot - a fork rewritten in Rust{{Citation |title=oreboot/oreboot |date=2025-03-27 |url=https://github.com/oreboot/oreboot |access-date=2025-03-31 |publisher=oreboot}} == See also == {{Portal|Free and open-source software}} * [Beowulf cluster](/source/Beowulf_cluster) * [LinuxBoot](/source/LinuxBoot) * [Open-source hardware](/source/Open-source_hardware) * [Rapid Boot](/source/Rapid_Boot) == References == {{Reflist}} == Further reading == * [https://developer.ibm.com/articles/l-linuxboot/ Inside the Linux boot process], by M. Jones, IBM * [https://web.archive.org/web/20170104233908/https://www.ibm.com/developerworks/linux/library/l-bios/ Open BIOSes for Linux], by Peter Seebach (archive only) * [https://web.archive.org/web/20070110135736/http://www.linux.com/article.pl?sid=06%2F11%2F30%2F199208 LinuxBIOS ready to go mainstream], by Bruce Byfield * [https://lkml.org/lkml/2007/2/21/490 First desktop motherboard supported by LinuxBIOS: GIGABYTE M57SLI-S4], by Brandon Howard * [https://web.archive.org/web/20070928142218/http://ftp.belnet.be/mirrors/FOSDEM/2007/FOSDEM2007-LinuxBios.ogg Video recording of Ron Minnich's LinuxBIOS talk from FOSDEM 2007] * [http://www.linuxjournal.com/magazine/coreboot-your-service Coreboot Your Service], [Linux Journal](/source/Linux_Journal), October 2009 * [https://media.ccc.de/search?q=Peter+Stuge media.ccc.de - Search for "Peter Stuge"] == External links == * {{commonscatinline}} * {{Official website}} {{Firmware and booting}} Category:Custom firmware Category:Firmware Category:Free BIOS implementations Category:Software related to embedded Linux --- Adapted from the Wikipedia article [Coreboot](https://en.wikipedia.org/wiki/Coreboot) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Coreboot?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.