# Chiplet

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{{Short description|Tiny integrated circuit with a well-defined function}}
A '''chiplet'''<ref>{{cite web |url=https://www.howtogeek.com/740584/what-is-a-chiplet/ |title=What Is a Chiplet? |last=Brookes |date=25 July 2021 |website=How-To Geek |access-date=28 December 2021}}</ref><ref>{{cite web |url=https://en.wikichip.org/wiki/chiplet |title=Chiplet |website=WikiChip |access-date=28 December 2021}}</ref><ref>AnySilicon "[https://anysilicon.com/the-ultimate-guide-to-chiplets/ The Ultimate Guide to Chiplets]" Retrieved 23 December 2024</ref><ref>Don Scansen, EE Times "[https://www.eetimes.com/chiplets-a-short-history/ Chiplets: A Short History] Retrieved 5 December 2022</ref> is a tiny [integrated circuit](/source/integrated_circuit) ('''IC''') that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an [interposer](/source/interposer) in a single [package](/source/electronic_packaging) to create a complex component such as a computer processor. Each chiplet in a computer processor provides only a portion of the processor's total functionality. A set of chiplets can be implemented in a mix-and-match "[Lego](/source/Lego)-like" assembly. This provides several advantages over a traditional [system on chip](/source/system_on_a_chip) ('''SoC''') which is monolithic as it comprises a single silicon die:

* Reusable IP (intellectual property):<ref>{{cite web |url=https://www.darpa.mil/program/common-heterogeneous-integration-and-ip-reuse-strategies |title=Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) |last=Keeler |website=DARPA |access-date=28 December 2021}}</ref> the same chiplet can be used in many different devices
* Heterogeneous integration:<ref>{{cite web |url=https://www.eetimes.eu/heterogeneous-integration-and-the-evolution-of-ic-packaging/ |title=Heterogeneous Integration and the Evolution of IC Packaging |last=Kenyon |date=6 April 2021 |website=EE Times Europe |access-date=28 December 2021}}</ref> chiplets can be fabricated with different processes, materials, and [node](/source/process_node)s, each optimized for its particular function
* Known good die:<ref>{{cite book |chapter-url=https://link.springer.com/chapter/10.1007/978-1-4615-1389-6_4 |access-date=7 October 2022 |publisher=SpringerLink|year=2001 |doi=10.1007/978-1-4615-1389-6_4 |last1=Bertin |first1=Claude L. |last2=Su |first2=Lo-Soun |last3=Van Horn |first3=Jody |title=Area Array Interconnection Handbook |chapter=Known Good die (KGD) |pages=149–200 |isbn=978-1-4613-5529-8 }}</ref> chiplets can be tested before assembly, improving the yield of the final device.

Multiple chiplets working together in a single integrated circuit may be called a [multi-chip module](/source/multi-chip_module), [hybrid IC](/source/hybrid_integrated_circuit), [2.5D IC](/source/2.5D_integrated_circuit), or an [advanced package](/source/advanced_packaging_(semiconductors)).

Chiplets may be connected with standards such as [UCIe](/source/UCIe), bunch of wires (BoW), AIB (Advanced Interface Bus), OpenHBI (Open High Bandwidth Interface), and OIF (Optical Internetworking Forum) XSR (Extra Short Reach).<ref>{{cite web | url=https://semiengineering.com/waiting-for-chiplet-standards/ | title=Waiting for Chiplet Standards | date=25 March 2021 }}</ref><ref>{{cite web | url=https://semiengineering.com/is-ucie-really-universal/#comment-1094750 | title=Is UCIe Really Universal? | date=22 November 2022 }}</ref> Chiplets not designed by the same company must be designed with interoperability in mind.<ref>{{cite web | url=https://semiengineering.com/ucie-goes-back-to-the-drawing-board/ | title=UCIe Goes Back to the Drawing Board | date=22 February 2024 }}</ref>

The term was coined by [University of California, Berkeley](/source/University_of_California%2C_Berkeley) professor [John Wawrzynek](/source/John_Wawrzynek) as a component of the RAMP Project (research accelerator for multiple processors) in 2006 <ref>{{Cite book |last=Patterson |first=D.A. |title=2006 IEEE International Symposium on Performance Analysis of Systems and Software |chapter=RAMP: Research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform |date=March 2006 |pages=1– |doi=10.1109/ISPASS.2006.1620784|isbn=1-4244-0186-0 }}</ref><ref>{{Cite journal |last=Wawrzynek |first=John |date=2015-05-01 |title=Accelerating Science Driven System Design With RAMP |osti=1186854 |url=https://www.osti.gov/biblio/1186854 |language=English |journal=UCB|doi=10.2172/1186854 |url-access=subscription }}</ref> extension for the [Department of Energy](/source/United_States_Department_of_Energy).

Common examples include:

* AMD [Ryzen](/source/Ryzen) based on [Zen 2](/source/Zen_2) and later architecture (except APUs<ref> {{Cite web |last=crmaris |date=2024-01-29 |title=AMD Ryzen 7 8700G APU Review: Performance, Thermals & Power Analysis |url=https://hwbusters.com/cpu/amd-ryzen-7-8700g-apu-review-performance-thermals-power-analysis/ |access-date=2025-12-24 |website=Hardware Busters |language=en-US}}</ref>)
* [NVidia H100](/source/Hopper_(microarchitecture)), and later
* Intel [Sapphire Rapids](/source/Sapphire_Rapids) / [Meteor Lake](/source/Meteor_Lake) / [Arrow Lake](/source/Arrow_Lake_(microprocessor)), and later

==See also==
*[UCIe](/source/UCIe)
*[Multi-chip module](/source/Multi-chip_module) 

==References==
{{Reflist}}

==Further reading==
* {{cite news |last=Clark |first=Don |date=11 May 2023 |title=U.S. Focuses on Invigorating 'Chiplets' to Stay Cutting-Edge in Tech |url=https://www.nytimes.com/2023/05/11/technology/us-chiplets-tech.html |work=[The New York Times](/source/The_New_York_Times)}}

Category:Integrated circuits
Category:Semiconductor devices

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Adapted from the Wikipedia article [Chiplet](https://en.wikipedia.org/wiki/Chiplet) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Chiplet?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.