# Bus mastering

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System for multiple bus access

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In [computing](/source/Computing), **bus mastering** is a feature supported by many [bus architectures](/source/Bus_(computing)) that enables a device connected to the bus to initiate [direct memory access](/source/Direct_memory_access) (DMA) transactions. It is also referred to as **first-party DMA**, in contrast with [third-party DMA](/source/Third-party_DMA) where a system [DMA controller](/source/DMA_controller) actually does the transfer.

Some types of buses allow only one device (typically the [CPU](/source/Central_processing_unit), or its proxy) to initiate transactions. Most modern bus architectures, such as [PCI](/source/Peripheral_Component_Interconnect), allow multiple devices to bus master because it significantly improves performance for general-purpose [operating systems](/source/Operating_system). Some [real-time operating systems](/source/Real-time_operating_system) prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency.

While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to [main memory](/source/Main_memory).

If multiple devices are able to master the bus, there needs to be a **bus arbitration** scheme to prevent multiple devices attempting to drive the bus simultaneously. A number of different schemes are used for this; for example [SCSI](/source/SCSI) has a fixed priority for each SCSI ID. PCI does not specify the algorithm to use, leaving it up to the implementation to set priorities.

## See also

- [Master/slave (technology)](/source/Master%2Fslave_(technology))

- [SCSI initiator and target](/source/SCSI_initiator_and_target)

## References

- [How Bus Mastering Works](http://www.tweak3d.net/articles/howbusmaster/) - Tweak3D

- [What is bus mastering?](https://web.archive.org/web/20120316232747/http://bugclub.org/beginners/hardware/BUSMastering.html)- Brevard User's Group

v t e Technical and de facto standards for wired computer buses General System bus Front-side bus Back-side bus Daisy chain Control bus Address bus Bus contention Bus mastering Network on a chip Plug and play Double data rate Quad data rate List of bus bandwidths Standards SS-50 bus S-100 bus Multibus Unibus VAXBI MBus STD Bus SMBus Q-Bus Europe Card Bus ISA STEbus Zorro II Zorro III CAMAC FASTBUS LPC HP Precision Bus EISA VME VXI VXS VPX NuBus TURBOchannel MCA SBus VLB HP GSC bus InfiniBand Ethernet UPA PCI PCI Extended (PCI-X) PXI PCI Express (PCIe) AGP Compute Express Link (CXL) Direct Media Interface (DMI) RapidIO Intel QuickPath Interconnect NVLink HyperTransport Infinity Fabric Intel Ultra Path Interconnect Coherent Accelerator Processor Interface (CAPI) SpaceWire Storage ST-506 ESDI SDI IPI SMD Floppy connector Parallel ATA (PATA) Bus and Tag DSSI HIPPI Serial ATA (SATA) SCSI Parallel SAS ESCON Fibre Channel SSA SATAe PCI Express (via AHCI or NVMe logical device interface) Peripheral Apple Desktop Bus Atari SIO DCB Commodore bus HP-IL HIL MIDI RS-232 RS-422 RS-423 RS-485 Lightning DMX512-A IEEE-488 (GPIB) IEEE-1284 (parallel port) IEEE-1394 (FireWire) UNI/O 1-Wire I²C (ACCESS.bus, PMBus, SMBus) I3C SPI D²B Parallel SCSI Profibus USB Camera Link External PCIe Thunderbolt CAN bus Audio ADAT Lightpipe AES3 Intel HD Audio I2S MADI McASP S/PDIF TOSLINK Portable PC Card ExpressCard Embedded Multidrop bus CoreConnect AMBA (AXI) Wishbone SLIMbus Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest. Category

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Adapted from the Wikipedia article [Bus mastering](https://en.wikipedia.org/wiki/Bus_mastering) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Bus_mastering?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.