# Bus (computing) > Mediated Wiki article. Canonical URL: https://mediated.wiki/source/Bus_(computing) > Markdown URL: https://mediated.wiki/source/Bus_(computing).md > Source: https://en.wikipedia.org/wiki/Bus_(computing) > Source revision: 1357130089 > License: Creative Commons Attribution-ShareAlike 4.0 International (https://creativecommons.org/licenses/by-sa/4.0/) Data transfer channel connecting parts of a computer This article is about buses in computer hardware. For buses in software, see [Software bus](/source/Software_bus). Four [PCI Express](/source/PCI_Express) bus card slots (from top to second from bottom: ×4, ×16, ×1 and ×16), compared to a 32-bit [conventional PCI](/source/Conventional_PCI) bus card slot (very bottom) In [computer architecture](/source/Computer_architecture), a **bus** (historically also called a **data highway**[1] or **databus**) is a communication system that transfers [data](/source/Data_(computing)) between components inside a [computer](/source/Computer) or between computers.[2] It encompasses both [hardware](/source/Computer_hardware) (e.g., wires, [optical fiber](/source/Optical_fiber)) and [software](/source/Software), including [communication protocols](/source/Communication_protocol).[3] At its core, a bus is a shared physical pathway, typically composed of wires or traces on a circuit board, that allows multiple devices to communicate. To prevent conflicts and ensure orderly data exchange, buses rely on a communication protocol to manage which device can transmit data at a given time. Buses are categorized based on their role, such as [system buses](/source/System_bus) (also known as internal buses, internal data buses, or memory buses) connecting the [CPU](/source/CPU) and [memory](/source/Computer_memory). [Expansion buses](/source/Expansion_bus), also called [peripheral buses](/source/Peripheral_bus), extend the system to connect additional devices, including [peripherals](/source/Peripheral). Examples of widely used buses include [PCI Express](/source/PCI_Express) (PCIe) for high-speed internal connections and [Universal Serial Bus](/source/Universal_Serial_Bus) (USB) for connecting external devices. Modern buses utilize both [parallel](/source/Parallel_communication) and [serial communication](/source/Serial_communication), employing advanced encoding methods to maximize speed and efficiency. Features such as [direct memory access](/source/Direct_memory_access) (DMA) further enhance performance by allowing data transfers directly between devices and memory without requiring CPU intervention. ## Address bus This section does not cite any sources. Please help improve this section by adding citations to reliable sources. Unsourced material may be challenged and removed. (June 2023) (Learn how and when to remove this message) An *address bus* is a bus that is used to specify a [physical address](/source/Physical_address). When a [processor](/source/Central_processing_unit) or [DMA](/source/Direct_memory_access)-enabled device needs to read or write to a memory location, it specifies that memory location on the address bus (the value to be read or written is sent on the data bus).[4] The width of the address bus determines the amount of memory a system can transfer simultaneously.[5] For example, a system with a *32-bit* address bus can address *232* (4,294,967,296) memory locations.[6] If each memory location holds one byte, the addressable memory space is about 4 [GB](/source/Gigabyte). ### Address multiplexing Early processors used a wire for each bit of the address width. For example, a 16-bit address bus had 16 physical wires making up the bus. As the buses became wider and longer, this approach became expensive in terms of the number of chip pins and board traces. Beginning with the [Mostek](/source/Mostek) 4096 [DRAM](/source/DRAM), address multiplexing implemented with [multiplexers](/source/Multiplexer) became common.[7] In a multiplexed address scheme, the address is sent in two equal parts on alternate bus cycles. This halves the number of address bus signals required to connect to the memory. For example, a 32-bit address bus can be implemented by using 16 lines and sending the first half of the memory address, immediately followed by the second half of the memory address. Typically, two additional pins in the control bus – row-address strobe (RAS) and column-address strobe (CAS) – are used to tell the DRAM whether the address bus is currently sending the first half of the memory address or the second half. ### Implementation Accessing an individual byte frequently requires reading or writing the full bus width (a [word](/source/Word_(data_type))) at once. In these instances, the least significant bits of the address bus may not even be implemented - it is instead the responsibility of the controlling device to isolate the individual byte required from the complete word transmitted. This is the case, for instance, with the [VESA Local Bus](/source/VESA_Local_Bus), which lacks the two least significant bits, limiting this bus to [aligned](/source/Data_structure_alignment) 32-bit transfers. Historically, there were also some examples of computers that were only able to address words – [word machines](/source/Word_machine). ## Memory bus This section does not cite any sources. Please help improve this section by adding citations to reliable sources. Unsourced material may be challenged and removed. (June 2023) (Learn how and when to remove this message) The *memory bus* is the bus that connects the [main memory](/source/Main_memory) to the [memory controller](/source/Memory_controller) in computer systems. Originally, general-purpose buses like [VMEbus](/source/VMEbus) and the [S-100 bus](/source/S-100_bus) were used, but to reduce [latency](/source/Latency_(engineering)), modern memory buses are designed to connect directly to DRAM chips, and thus are defined by chip standards bodies such as [JEDEC](/source/JEDEC). Examples are the various generations of [SDRAM](/source/SDRAM), and serial point-to-point buses like [SLDRAM](/source/SLDRAM) and [RDRAM](/source/RDRAM). ## Implementation details Buses can be [parallel buses](/source/Parallel_bus), which carry [data words](/source/Data_word) in parallel on multiple wires, or [serial buses](/source/Serial_bus), which carry data in bit-serial form. The addition of extra power and control connections, [differential drivers](/source/Differential_signaling), and data connections in each direction usually means that most serial buses have more conductors than the minimum of one used in [1-Wire](/source/1-Wire) and [UNI/O](/source/UNI%2FO). As data rates increase, the problems of [timing skew](/source/Timing_skew), power consumption, electromagnetic interference and [crosstalk](/source/Crosstalk) across parallel buses become more and more difficult to circumvent. One partial solution to this problem has been to [double pump](/source/Double_pump) the bus. Often, a serial bus can be operated at higher overall data rates than a parallel bus, despite having fewer electrical connections, because a serial bus inherently has no timing skew or crosstalk. [USB](/source/USB), [FireWire](/source/FireWire), and [Serial ATA](/source/Serial_ATA) are examples of this. [Multidrop](/source/Multidrop) connections do not work well for fast serial buses, so most modern serial buses use [daisy-chain](/source/Daisy_chain_(information_technology)#Computer_hardware) or hub designs. The transition from parallel to serial buses was allowed by [Moore's law](/source/Moore's_law) which allowed for the incorporation of [serializer/deserializers](/source/SerDes) in integrated circuits which are used in computers.[8] [Network](/source/Computer_network) connections such as [Ethernet](/source/Ethernet) are not generally regarded as buses, although the difference is largely conceptual rather than practical. An attribute generally used to characterize a bus is that power is provided by the bus for the connected hardware. This emphasizes the [busbar](/source/Busbar) origins of bus architecture as supplying switched or distributed power. This excludes, as buses, schemes such as serial [RS-232](/source/RS-232), parallel [Centronics](/source/Centronics), [IEEE 1284](/source/IEEE_1284) interfaces and Ethernet, since these devices also needed separate power supplies. [Universal Serial Bus](/source/Universal_Serial_Bus) devices may use the bus-supplied power, but often use a separate power source. This distinction is exemplified by a [telephone](/source/Plain_old_telephone_service) system with a connected [modem](/source/Modem), where the [RJ11](/source/RJ11) connection and associated modulated signalling scheme is not considered a bus, and is analogous to an [Ethernet](/source/Ethernet) connection. A phone line connection scheme is not considered to be a bus with respect to signals, but the [Central Office](/source/Telephone_exchange) uses buses with [cross-bar switches](/source/Cross-bar_switch) for connections between phones. However, this distinction‍—‌that power is provided by the bus‍—‌is not the case in many [avionic systems](/source/Avionics), where data connections such as [ARINC 429](/source/ARINC_429), [ARINC 629](/source/ARINC_629), [MIL-STD-1553B](/source/MIL-STD-1553B) (STANAG 3838), and EFABus ([STANAG 3910](/source/STANAG_3910)) are commonly referred to as *data buses* or, sometimes, *databuses*. Such [avionic data buses](/source/Avionics#Aircraft_networks) are usually characterized by having several [Line Replaceable Items/Units](/source/Line-replaceable_unit) (LRI/LRUs) connected to a common, shared [media](/source/Media_(communication)). They may, as with ARINC 429, be [simplex](/source/Simplex_communication), i.e., have a single source LRI/LRU or, as with ARINC 629, MIL-STD-1553B, and STANAG 3910, be [duplex](/source/Duplex_(telecommunications)), allowing all the connected LRI/LRUs to act, at different times ([half duplex](/source/Half_duplex)), as transmitters and receivers of data.[9] The frequency or the speed of a bus is measured in Hz, such as MHz, and determines how many clock cycles there are per second; there can be one or more data transfers per clock cycle. If there is a single transfer per clock cycle, it is known as [Single Data Rate](https://en.wikipedia.org/w/index.php?title=Single_Data_Rate&action=edit&redlink=1) (SDR), and if there are two transfers per clock cycle, it is known as [Double Data Rate](/source/Double_Data_Rate) (DDR), although the use of signaling other than SDR is uncommon outside of RAM. An example of this is PCIe, which uses SDR.[10] Within each data transfer, there can be multiple bits of data. This is described as the width of a bus, which is the number of bits the bus can transfer per clock cycle and can be synonymous with the number of physical electrical conductors the bus has if each conductor transfers one bit at a time.[11][12][13] The data rate in bits per second can be obtained by multiplying the number of bits per clock cycle times the frequency times the number of transfers per clock cycle.[14][15] Alternatively a bus such as [PCIe](/source/PCIe) can use modulation or encoding such as [PAM4](/source/PAM4)[16][17][18] which groups 2 bits into symbols which are then transferred instead of the bits themselves, and allows for an increase in data transfer speed without increasing the frequency of the bus. The effective or real data transfer speed/rate may be lower due to the use of encoding that also allows for error correction, such as 128/130b (b for bit) encoding.[19][20][10] The data transfer speed is also known as the bandwidth.[21][22] ### Bus multiplexing Main article: [Bus encoding § Other examples of bus encoding](/source/Bus_encoding#Other_examples_of_bus_encoding) The simplest [system bus](/source/System_bus) has completely separate input data lines, output data lines, and address lines. To reduce cost, most microcomputers have a bidirectional data bus, reusing the same wires for input and output at different times.[23] Some processors use a dedicated wire for each bit of the address bus, data bus, and control bus. For example, the 64-pin [STEbus](/source/STEbus) is composed of 8 physical wires dedicated to the 8-bit data bus, 20 physical wires dedicated to the 20-bit address bus, 21 physical wires dedicated to the control bus, and 15 physical wires dedicated to various power buses. Bus multiplexing requires fewer wires, which reduces costs in many early microprocessors and DRAM chips. One common multiplexing scheme, [address multiplexing](#Address_multiplexing), has already been mentioned. Another multiplexing scheme re-uses the address bus pins as the data bus pins,[23] an approach used by [conventional PCI](/source/Conventional_PCI) and the [8086](/source/8086). The various *serial buses* can be seen as the ultimate limit of multiplexing, sending each of the address bits and each of the data bits, one at a time, through a single pin (or a single differential pair). ## History Over time, several groups of people worked on various computer bus standards, including the IEEE Bus Architecture Standards Committee (BASC), the IEEE Superbus study group, the open microprocessor initiative (OMI), the open microsystems initiative (OMI), the *[Gang of Nine](/source/Gang_of_Nine)* that developed [EISA](/source/Extended_Industry_Standard_Architecture), etc.[*[citation needed](https://en.wikipedia.org/wiki/Wikipedia:Citation_needed)*] ### First generation Early [computer](/source/Computer) buses were bundles of wire that attached [computer memory](/source/Computer_memory) and peripherals. Anecdotally termed the *digit trunk* in the early Australian [CSIRAC](/source/CSIRAC) computer,[24] they were named after electrical power buses, or [busbars](/source/Busbar). Almost always, there was one bus for memory, and one or more separate buses for peripherals. These were accessed by separate instructions, with completely different timings and protocols. One of the first complications was the use of [interrupts](/source/Interrupt). Early computer programs performed [I/O](/source/I%2FO) by [waiting in a loop](/source/Busy_waiting) for the peripheral to become ready. This was a waste of time for programs that had other tasks to do. Also, if the program attempted to perform those other tasks, it might take too long for the program to check again, resulting in loss of data. Engineers thus arranged for the peripherals to interrupt the [CPU](/source/CPU). The interrupts had to be prioritized because the CPU can only execute code for one peripheral at a time, and some devices are more time-critical than others. High-end systems introduced the idea of [channel controllers](/source/Channel_controller), which were essentially small computers dedicated to handling the input and output of a given bus. [IBM](/source/IBM) introduced these on the [IBM 709](/source/IBM_709) in 1958, and they became a common feature of their platforms. Other high-performance vendors like [Control Data Corporation](/source/Control_Data_Corporation) implemented similar designs. Generally, the channel controllers would do their best to run all of the bus operations internally, moving data when the CPU was known to be busy elsewhere if possible, and only using interrupts when necessary. This greatly reduced CPU load and provided better overall system performance. Single [system bus](/source/System_bus) To provide modularity, memory and I/O buses can be combined into a unified [system bus](/source/System_bus).[25] In this case, a single mechanical and electrical system can be used to connect together many of the system components, or in some cases, all of them. Later computer programs began to share memory common to several CPUs. Access to this memory bus had to be prioritized, as well. The simple way to prioritize interrupts or bus access was with a [daisy chain](/source/Daisy_chain_(electrical_engineering)). In this case, signals will naturally flow through the bus in physical or logical order, eliminating the need for complex scheduling. ### Minis and micros [Digital Equipment Corporation](/source/Digital_Equipment_Corporation) (DEC) further reduced cost for mass-produced [minicomputers](/source/Minicomputer), and [mapped peripherals](/source/Memory-mapped_I%2FO) into the memory bus, so that the input and output devices appeared to be memory locations. This was implemented in the [Unibus](/source/Unibus) of the [PDP-11](/source/PDP-11) around 1969.[26] Early [microcomputer](/source/Microcomputer) bus systems were essentially a passive [backplane](/source/Backplane) connected directly or through buffer amplifiers to the pins of the CPU. Memory and other devices would be added to the bus using the same address and data pins as the CPU itself used, connected in parallel. Communication was controlled by the CPU, which read and wrote data from the devices as if they were blocks of memory, using the same instructions, all timed by a central clock controlling the speed of the CPU. Still, devices [interrupted](/source/Interrupt) the CPU by signaling on separate CPU pins. For instance, a [disk drive](/source/Disk_drive) controller would signal the CPU that new data was ready to be read, at which point the CPU would move the data by reading the memory location that corresponded to the disk drive. Almost all early microcomputers were built in this fashion, starting with the [S-100 bus](/source/S-100_bus) in the [Altair 8800](/source/Altair_8800) computer system. In some instances, most notably in the [IBM PC](/source/IBM_PC), although similar physical architecture can be employed, instructions to access peripherals (in and out) and memory (mov and others) have not been made uniform at all, and still generate distinct CPU signals, that could be used to implement a separate I/O bus. These simple bus systems had a serious drawback when used for general-purpose computers. All the equipment on the bus had to talk at the same speed, as it shared a single clock. Increasing the speed of the CPU becomes harder because the speed of all the devices must increase as well. When it is not practical or economical to have all devices as fast as the CPU, the CPU must either enter a [wait state](/source/Wait_state), or work at a slower clock frequency temporarily,[27] to talk to other devices in the computer. While acceptable in [embedded systems](/source/Embedded_systems), this problem was not tolerated for long in general-purpose, user-expandable computers. Such bus systems are also difficult to configure when constructed from common off-the-shelf equipment. Typically, each added [expansion card](/source/Expansion_card) requires many [jumpers](/source/Jumper_(computing)) in order to set memory addresses, I/O addresses, interrupt priorities, and interrupt numbers. ### Second generation This section does not cite any sources. Please help improve this section by adding citations to reliable sources. Unsourced material may be challenged and removed. (June 2023) (Learn how and when to remove this message) Second-generation bus systems like [NuBus](/source/NuBus) addressed some of these problems. They typically separated the computer into two [address spaces](/source/Address_space), the CPU and memory on one side, and the various peripheral devices on the other. A *bus controller* accepted data from the CPU side to be moved to the peripherals side, thus shifting the communications protocol burden from the CPU itself. This allowed the CPU and memory side to evolve separately from the peripheral bus. Devices on the bus could talk to each other with no CPU intervention. This led to much better performance but also required the cards to be much more complex. These buses also often addressed speed issues by being bigger in terms of the size of the data path, moving from 8-bit [parallel buses](/source/Parallel_bus) in the first generation, to 16 or 32-bit in the second, as well as adding software setup (later standardized as [Plug-n-play](/source/Plug-n-play)) to supplant or replace the jumpers. However, these newer systems shared one quality with their earlier cousins, in that everyone on the bus had to talk at the same speed. While the CPU was now isolated and could increase speed, CPUs and memory continued to increase in speed much faster than the buses they talked to. The result was that the bus speeds were now much slower than what a modern system needed, and the machines were left starved for data. A particularly common example of this problem was that [video cards](/source/Video_card) quickly outran even the newer bus systems like [PCI](/source/PCI_Local_Bus), and computers began to include [AGP](/source/Accelerated_Graphics_Port) just to drive the video card. By 2004, AGP was outgrown again by high-end video cards and other peripherals and had been replaced by the new [PCI Express](/source/PCI_Express) bus. An increasing number of external devices started employing their own bus systems as well. When disk drives were first introduced, they would be added to the machine with a card plugged into the bus, which is why computers have so many slots on the bus. But through the 1980s and 1990s, new systems like [SCSI](/source/SCSI) and [IDE](/source/Integrated_Drive_Electronics) were introduced to serve this need, leaving most slots in modern systems empty. Today, there are likely to be about five different buses in the typical machine, supporting various devices.[*[citation needed](https://en.wikipedia.org/wiki/Wikipedia:Citation_needed)*] ### Third generation See also: [Bus network](/source/Bus_network) Third-generation buses have been emerging into the market since about 2001, including [HyperTransport](/source/HyperTransport) and [InfiniBand](/source/InfiniBand). They also tend to be very flexible in terms of their physical connections, allowing them to be used both as internal buses as well as connecting different machines together. This can lead to complex problems when trying to service different requests, so much of the work on these systems concerns software design, as opposed to the hardware itself. In general, these third-generation buses tend to look more like a [network](/source/Computer_network) than the original concept of a bus, with a higher protocol overhead needed than early systems, while also allowing multiple devices to use the bus at once. Buses such as [Wishbone](/source/Wishbone_(computer_bus)) have been developed by the [open source hardware](/source/Open_source_hardware) movement in an attempt to further remove legal and patent constraints from computer design. The [Compute Express Link](/source/Compute_Express_Link) (CXL) is an [open standard](/source/Open_standard) [interconnect](/source/Interconnect) for high-speed CPU-to-device and CPU-to-memory, designed to accelerate next-generation [data center](/source/Data_center) performance.[28] ## Examples of internal computer buses ### Parallel - [Asus Media Bus](/source/Asus_Media_Bus) proprietary, used on some [Asus](/source/Asus) [Socket 7](/source/Socket_7) motherboards - [Computer Automated Measurement and Control](/source/Computer_Automated_Measurement_and_Control) (CAMAC) for instrumentation systems - [Extended ISA](/source/Extended_ISA) or EISA - [GSC/HSC](/source/GSC_bus), a proprietary peripheral bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family - [Industry Standard Architecture](/source/Industry_Standard_Architecture) or ISA - [Low Pin Count](/source/Low_Pin_Count) or LPC - [MBus](/source/MBus_(SPARC)) - [MicroChannel](/source/MicroChannel) or MCA - [Multibus](/source/Multibus) for industrial systems - [NuBus](/source/NuBus) or IEEE 1196 - [OPTi local bus](https://en.wikipedia.org/w/index.php?title=OPTi_local_bus&action=edit&redlink=1) used on early [Intel 80486](/source/Intel_80486) motherboards.[29] - [Parallel ATA](/source/Parallel_ATA) (also known as Advanced Technology Attachment, ATA, PATA, IDE, EIDE, ATAPI, etc.), [Hard disk drive](/source/Hard_disk_drive), [optical disk drive](/source/Optical_disk_drive), [tape drive](/source/Tape_drive) peripheral attachment bus - [Peripheral Component Interconnect](/source/Peripheral_Component_Interconnect) or Conventional PCI - [PC/104](/source/PC%2F104) - [PC/104-Plus](/source/PC%2F104#PC/104-Plus) - [PCI-104](/source/PCI-104) - [PCI/104-Express](/source/PCI%2F104-Express) - [PCI/104](/source/PC%2F104#PCI/104) - [Precision Bus](/source/HP_Precision_Bus), a proprietary bus developed by Hewlett-Packard for use by its HP3000 computer family - [Q-Bus](/source/Q-Bus), a proprietary bus developed by [Digital Equipment Corporation](/source/Digital_Equipment_Corporation) for their [PDP](/source/Programmed_Data_Processor) and later [VAX](/source/VAX) computers. - [Runway bus](/source/Runway_bus), a proprietary front-side CPU bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family - [S-100 bus](/source/S-100_bus) or IEEE 696, used in the [Altair 8800](/source/Altair_8800) and similar [microcomputers](/source/Microcomputer) - [SBus](/source/SBus) or IEEE 1496 - [SS-50 Bus](/source/SS-50_Bus) - [STEbus](/source/STEbus) - [STD Bus](/source/STD_Bus) (for STD-80 [8-bit] and STD32 [16-/32-bit]), [FAQ](http://www.controlled.com/std/faq.html) [Archived](https://web.archive.org/web/20120227030406/http://www.controlled.com/std/faq.html) 2012-02-27 at the [Wayback Machine](/source/Wayback_Machine) - [Unibus](/source/Unibus), a proprietary bus developed by [Digital Equipment Corporation](/source/Digital_Equipment_Corporation) for their [PDP-11](/source/PDP-11) and early [VAX](/source/VAX) computers. - [VESA Local Bus](/source/VESA_Local_Bus) or VLB or VL-bus - [VMEbus](/source/VMEbus), the VERSAmodule Eurocard bus - [Zorro II](/source/Zorro_II) and [Zorro III](/source/Zorro_III), used in [Amiga](/source/Amiga) computer systems ### Serial - [1-Wire](/source/1-Wire) - [Advanced eXtensible Interface](/source/Advanced_eXtensible_Interface) - [HyperTransport](/source/HyperTransport) - [I²C](/source/I%C2%B2C) - [I3C (bus)](/source/I3C_(bus)) - [M-PHY](/source/M-PHY) - [PCI Express](/source/PCI_Express) or PCIe - [Serial ATA](/source/Serial_ATA) (SATA), [Hard disk drive](/source/Hard_disk_drive), [solid-state drive](/source/Solid-state_drive), [optical disc drive](/source/Optical_disc_drive), [tape drive](/source/Tape_drive) peripheral attachment bus - [Serial Peripheral Interface](/source/Serial_Peripheral_Interface) (SPI) bus - [SLIMbus](/source/SLIMbus) - [SMBus](/source/SMBus) - [UNI/O](/source/UNI%2FO) ## Examples of external computer buses ### Parallel - [HIPPI](/source/HIPPI) High Performance Parallel Interface - [IEEE-488](/source/IEEE-488) (also known as GPIB, General-Purpose Interface Bus, and HPIB, Hewlett-Packard Instrumentation Bus) - [PC Card](/source/PC_Card), previously known as *PCMCIA*, much used in laptop computers and other portables, but fading with the introduction of USB and built-in network and modem connections ### Serial Many [field buses](/source/Field_bus) are serial data buses (not to be confused with the parallel data bus section of a [system bus](/source/System_bus) or [expansion card](/source/Expansion_card)), several of which use the [RS-485](/source/RS-485) electrical characteristics and then specify their own protocol and connector: - [ARINC 429](/source/ARINC_429) - [CAN bus](/source/CAN_bus) ("Controller Area Network") - [IEEE 1355](/source/IEEE_1355) - [MIL-STD-1553](/source/MIL-STD-1553) - [Modbus](/source/Modbus) Other serial buses include: - [Camera Link](/source/Camera_Link) - [eSATA](/source/ESATA) - [ExpressCard](/source/ExpressCard) - [IEEE 1394 interface](/source/IEEE_1394_interface) (FireWire) - [RS-232](/source/RS-232) - [Thunderbolt](/source/Thunderbolt_(interface)) - [USB](/source/USB) ## Examples of internal/external computer buses - [Futurebus](/source/Futurebus) - [InfiniBand](/source/InfiniBand) - [PCI Express External Cabling](/source/PCI_Express_External_Cabling) - [QuickRing](/source/QuickRing) - [Scalable Coherent Interface](/source/Scalable_Coherent_Interface) (SCI) - [Small Computer System Interface](/source/Small_Computer_System_Interface) (SCSI), [Hard disk drive](/source/Hard_disk_drive) and [tape drive](/source/Tape_drive) peripheral attachment bus - [Serial Attached SCSI](/source/Serial_Attached_SCSI) (SAS) and other [serial SCSI buses](/source/Serial_SCSI_buses) - [Thunderbolt](/source/Thunderbolt_(interface)) - Yapbus, a proprietary bus developed for the [Pixar Image Computer](/source/Pixar_Image_Computer) ## See also - [Electronics portal](https://en.wikipedia.org/wiki/Portal:Electronics) - [Address decoder](/source/Address_decoder) - [Bus contention](/source/Bus_contention) - [Bus error](/source/Bus_error) - [Bus mastering](/source/Bus_mastering) - [Communication endpoint](/source/Communication_endpoint) - [Computer port (hardware)](/source/Computer_port_(hardware)) - [Control bus](/source/Control_bus) - [Crossbar switch](/source/Crossbar_switch) - [External Bus Interface](/source/External_Bus_Interface) (EBI) - [Front-side bus](/source/Front-side_bus) (FSB) - [Harvard architecture](/source/Harvard_architecture) - [List of device bandwidths](/source/List_of_device_bandwidths) - [List of network buses](/source/List_of_network_buses) - [Master/slave (technology)](/source/Master%2Fslave_(technology)) - [Memory address](/source/Memory_address) - [Network on chip](/source/Network_on_chip) - [Software bus](/source/Software_bus) ## References 1. **[^](#cite_ref-Hollingdale_1958_1-0)** Hollingdale, Stuart H. (1958-09-19). [*Session 14. Data Processing*](https://www.chilton-computing.org.uk/acl/literature/othermanuals/nottingham/p014.htm). Applications of Computers, University of Nottingham 15–19 September 1958. 1. **[^](#cite_ref-2)** Clifton, Carl (1986-09-19). [*What Every Engineer Should Know about Data Communications*](https://books.google.com/books?id=YVi8HVN-APwC&q=computer+buss+-sam&pg=PA27). CRC Press. p. 27. [ISBN](/source/ISBN_(identifier)) [9780824775667](https://en.wikipedia.org/wiki/Special:BookSources/9780824775667). [Archived](https://web.archive.org/web/20180117151300/https://books.google.com/books?id=YVi8HVN-APwC&lpg=PA27&dq=computer%20buss%20-sam&pg=PA27#v=onepage&q=computer%20buss%20-sam&f=false) from the original on 2018-01-17. The internal computer bus is a parallel transmission scheme; within the computer.... 1. **[^](#cite_ref-3)** ["bus Definition from PC Magazine Encyclopedia"](https://www.pcmag.com/encyclopedia/term/39054/bus). pcmag.com. 2014-05-29. [Archived](https://web.archive.org/web/20150207204630/http://www.pcmag.com/encyclopedia/term/39054/bus) from the original on 2015-02-07. Retrieved 2014-06-21. 1. **[^](#cite_ref-4)** Gustavson, David (April 1984). [*Computer Buses: A Tutorial*](https://www.slac.stanford.edu/pubs/slacpubs/3250/slac-pub-3326.pdf) (PDF). 1. **[^](#cite_ref-5)** ["Difference Between System Bus and Address Bus"](https://www.geeksforgeeks.org/computer-organization-architecture/difference-between-system-bus-and-address-bus/). *GeeksForGeeks*. 2025-07-23. 1. **[^](#cite_ref-6)** ["Operating Systems"](https://www.sciencedirect.com/science/chapter/referencework/abs/pii/B0122274105008516). 2003-01-01: 169–191. [doi](/source/Doi_(identifier)):[10.1016/B0-12-227410-5/00851-6](https://doi.org/10.1016%2FB0-12-227410-5%2F00851-6). {{[cite journal](https://en.wikipedia.org/wiki/Template:Cite_journal)}}: Cite journal requires |journal= ([help](https://en.wikipedia.org/wiki/Help:CS1_errors#missing_periodical)) 1. **[^](#cite_ref-7)** ["Chip Hall of Fame: Mostek MK4096 4-Kilobit DRAM - IEEE Spectrum"](https://spectrum.ieee.org/chip-hall-of-fame-mostek-mk4096-4kilobit-dram). *spectrum.ieee.org*. Retrieved 2025-11-13. 1. **[^](#cite_ref-8)** [*The Boundary — Scan Handbook*](https://books.google.com/books?id=aUCgNOpyUbgC&dq=parallel++serial++serdes+moore%27s+law&pg=PA275). Springer. 2003-06-30. [ISBN](/source/ISBN_(identifier)) [978-1-4020-7496-7](https://en.wikipedia.org/wiki/Special:BookSources/978-1-4020-7496-7). 1. **[^](#cite_ref-ASSC_2003_9-0)** Avionic Systems Standardisation Committee, *Guide to Digital Interface Standards For Military Avionic Applications*, ASSC/110/6/2, Issue 2, September 2003 1. ^ [***a***](#cite_ref-IBM_z15_8561_Technical_Guide_10-0) [***b***](#cite_ref-IBM_z15_8561_Technical_Guide_10-1) [*IBM z15 (8561) Technical Guide*](https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155). IBM Redbooks. 2022-07-13. [ISBN](/source/ISBN_(identifier)) [978-0-7384-5812-0](https://en.wikipedia.org/wiki/Special:BookSources/978-0-7384-5812-0). 1. **[^](#cite_ref-11)** [*Foundations of Computer Technology*](https://books.google.com/books?id=hDwDEAAAQBAJ&dq=bus+width&pg=PA54). CRC Press. 2020-10-25. [ISBN](/source/ISBN_(identifier)) [978-1-000-11716-5](https://en.wikipedia.org/wiki/Special:BookSources/978-1-000-11716-5). 1. **[^](#cite_ref-12)** Beales, R. P. (2006-08-11). [*PC Systems, Installation and Maintenance*](https://books.google.com/books?id=j0wsBgAAQBAJ&dq=computer+bus+frequency&pg=PA39). Routledge. [ISBN](/source/ISBN_(identifier)) [978-1-136-37442-5](https://en.wikipedia.org/wiki/Special:BookSources/978-1-136-37442-5). 1. **[^](#cite_ref-13)** ["How Motherboards Work"](https://computer.howstuffworks.com/motherboard4.htm#:~:text=Bus%20speed%20usually%20refers%20to,dramatically%20affect%20a%20computer%27s%20performance). 2005-07-20. 1. **[^](#cite_ref-14)** Buchanan, Bill (2000-04-25). [*Computer Busses*](https://books.google.com/books?id=6FnMBQAAQBAJ&q=Data+rate&pg=PA92). CRC Press. [ISBN](/source/ISBN_(identifier)) [978-1-4200-4168-2](https://en.wikipedia.org/wiki/Special:BookSources/978-1-4200-4168-2). 1. **[^](#cite_ref-15)** Oklobdzija, Vojin G. (2019-07-05). [*The Computer Engineering Handbook*](https://books.google.com/books?id=vpnJDwAAQBAJ&q=Width). CRC Press. [ISBN](/source/ISBN_(identifier)) [978-1-4398-3316-2](https://en.wikipedia.org/wiki/Special:BookSources/978-1-4398-3316-2). 1. **[^](#cite_ref-16)** Robinson, Dan (2022-01-12). ["Final PCIe 6.0 specs unleashed: 64 GTps link speed incoming... with products to follow in 2023"](https://www.theregister.com/2022/01/12/final_pcie_60_specs_released/). *www.theregister.com*. 1. **[^](#cite_ref-17)** ["PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025"](https://web.archive.org/web/20240404125350/https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming). Archived from [the original](https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming) on 2024-04-04. 1. **[^](#cite_ref-18)** ["PCIe 5.0 is just beginning to come to new PCS, but version 6.0 is already here"](https://arstechnica.com/gadgets/2022/01/pci-express-6-0-spec-is-finalized-doubling-bandwidth-for-ssds-gpus-and-more/). 2022-01-12. 1. **[^](#cite_ref-19)** ["PCIe 6.0: Everything you need to know about the upcoming standard"](https://www.xda-developers.com/pcie-6/). 2024-06-30. 1. **[^](#cite_ref-20)** ["PAM-4 Signaling"](https://semiengineering.com/knowledge_centers/communications-io/off-chip-communications/pam-4-signaling/). 1. **[^](#cite_ref-21)** [*Upgrading and Repairing PCS*](https://books.google.com/books?id=eV1_LjW3pTkC&dq=agp+2133&pg=PA304). Que. 2003. [ISBN](/source/ISBN_(identifier)) [978-0-7897-2745-9](https://en.wikipedia.org/wiki/Special:BookSources/978-0-7897-2745-9). 1. **[^](#cite_ref-22)** ["PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025"](https://web.archive.org/web/20240404125350/https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming). Archived from [the original](https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming) on 2024-04-04. 1. ^ [***a***](#cite_ref-typewriter_23-0) [***b***](#cite_ref-typewriter_23-1) Don Lancaster. ["TV Typewriter Cookbook"](https://www.tinaja.com/ebooks/tvtcb.pdf). ([TV Typewriter](/source/TV_Typewriter)). Section "Bus Organization". p. 82. 1. **[^](#cite_ref-24)** McCann, Doug; Thorne, Peter (2000). [*The Last of The First, CSIRAC: Australias First Computer*](https://cis.unimelb.edu.au/about/csirac/last-of-the-first). University of Melbourne Computing Science. pp. 8–11, 13, 91. [ISBN](/source/ISBN_(identifier)) [0-7340-2024-4](https://en.wikipedia.org/wiki/Special:BookSources/0-7340-2024-4). 1. **[^](#cite_ref-25)** Linda Null; Julia Lobur (2006). [*The essentials of computer organization and architecture*](https://books.google.com/books?id=QGPHAl9GE-IC&pg=PA33) (2nd ed.). Jones & Bartlett Learning. pp. 33, 179–181. [ISBN](/source/ISBN_(identifier)) [978-0-7637-3769-6](https://en.wikipedia.org/wiki/Special:BookSources/978-0-7637-3769-6). [Archived](https://web.archive.org/web/20180117151308/https://books.google.com/books?id=QGPHAl9GE-IC&pg=PA33) from the original on 2018-01-17. 1. **[^](#cite_ref-26)** C. Gordon Bell; R. Cady; H. McFarland; B. Delagi; J. O'Laughlin; R. Noonan; W. Wulf (1970). [*A New Architecture for Mini-Computers—The DEC PDP-11*](http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf) (PDF). Spring Joint Computer Conference. pp. 657–675. [Archived](https://web.archive.org/web/20111127001221/http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf) (PDF) from the original on 2011-11-27. 1. **[^](#cite_ref-bray-aug_27-0)** Bray, Andrew C.; Dickens, Adrian C.; Holmes, Mark A. (1983). "28. The One Megahertz bus". [*The Advanced User Guide for the BBC Microcomputer*](https://web.archive.org/web/20060114042612/http://www.nvg.org/bbc/doc/BBCAdvancedUserGuide-PDF.zip). Cambridge, UK: Cambridge Microcomputer Centre. pp. 442–443. [ISBN](/source/ISBN_(identifier)) [0-946827-00-1](https://en.wikipedia.org/wiki/Special:BookSources/0-946827-00-1). Archived from [the original](http://www.nvg.org/bbc/doc/BBCAdvancedUserGuide-PDF.zip) (zipped PDF) on 2006-01-14. Retrieved 2008-03-28. 1. **[^](#cite_ref-28)** ["ABOUT CXL"](https://www.computeexpresslink.org/about-cxl). *Compute Express Link*. Retrieved 2019-08-09. 1. **[^](#cite_ref-29)** ["Odds & Ends: Opti Local Bus, Aria sound cards"](https://ancientelectronics.wordpress.com/tag/opti-local-bus/). 2015-07-21. Retrieved 2021-02-19. ## External links - [Computer hardware buses and slots pinouts with brief descriptions](http://pinouts.ru/pin_Slots.shtml) v t e Technical and de facto standards for wired computer buses General System bus Front-side bus Back-side bus Daisy chain Control bus Address bus Bus contention Bus mastering Network on a chip Plug and play Double data rate Quad data rate List of bus bandwidths Standards SS-50 bus S-100 bus Multibus Unibus VAXBI MBus STD Bus SMBus Q-Bus Europe Card Bus ISA STEbus Zorro II Zorro III CAMAC FASTBUS LPC HP Precision Bus EISA VME VXI VXS VPX NuBus TURBOchannel MCA SBus VLB HP GSC bus InfiniBand Ethernet UPA PCI PCI Extended (PCI-X) PXI PCI Express (PCIe) AGP Compute Express Link (CXL) Direct Media Interface (DMI) RapidIO Intel QuickPath Interconnect NVLink HyperTransport Infinity Fabric Intel Ultra Path Interconnect Coherent Accelerator Processor Interface (CAPI) SpaceWire Storage ST-506 ESDI SDI IPI SMD Floppy connector Parallel ATA (PATA) Bus and Tag DSSI HIPPI Serial ATA (SATA) SCSI Parallel SAS ESCON Fibre Channel SSA SATAe PCI Express (via AHCI or NVMe logical device interface) Peripheral Apple Desktop Bus Atari SIO DCB Commodore bus HP-IL HIL MIDI RS-232 RS-422 RS-423 RS-485 Lightning DMX512-A IEEE-488 (GPIB) IEEE-1284 (parallel port) IEEE-1394 (FireWire) UNI/O 1-Wire I²C (ACCESS.bus, PMBus, SMBus) I3C SPI D²B Parallel SCSI Profibus USB Camera Link External PCIe Thunderbolt CAN bus Audio ADAT Lightpipe AES3 Intel HD Audio I2S MADI McASP S/PDIF TOSLINK Portable PC Card ExpressCard Embedded Multidrop bus CoreConnect AMBA (AXI) Wishbone SLIMbus Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest. Category Authority control databases International GND National United States France BnF data Israel Other Yale LUX --- Adapted from the Wikipedia article [Bus (computing)](https://en.wikipedia.org/wiki/Bus_(computing)) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Bus_(computing)?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.