# Bit slicing

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{{Short description|Method of constructing a computer processor}}
{{Distinguish|Bit-banding}}
{{About|the [processor](/source/central_processing_unit) construction technique|bit slicing as ''bit plane separation'' used in computer graphics and image processing|Bit plane}}
{{Multiple issues|
{{Expand Russian|date=May 2017|topic=tech}}
{{Primary sources|date=January 2014}}
}}

{{Computer architecture bit widths}}
{{Use dmy dates|date=April 2020|cs1-dates=y}}
{{Use list-defined references|date=December 2021}}
'''Bit slicing''' is a technique for constructing a [processor](/source/Processor_(computing)) from modules of processors of smaller bit width, for the purpose of increasing the word length; in theory to make an arbitrary ''n''-bit [central processing unit](/source/central_processing_unit) (CPU). Each of these component modules processes one [bit field](/source/bit_field) or "slice" of an [operand](/source/operand). The grouped processing components would then have the capability to process the chosen full [word-length](/source/Word_(computer_architecture)) of a given software design.

Bit slicing more or less died out due to higher integration of the [microprocessor](/source/microprocessor). Recently it has been used in [arithmetic logic unit](/source/arithmetic_logic_unit)s (ALUs) for [quantum computer](/source/quantum_computer)s and as a software technique, e.g. for [cryptography](/source/cryptography) in [x86](/source/x86) CPUs.<ref name="Benadjila_2013"/>

== Operational details ==
Bit-slice processors (BSPs) usually include [1-](/source/1-bit_computing), [2-](/source/2-bit_computing), [4-](/source/4-bit_computing), [8-](/source/8-bit_computing) or [16-bit](/source/16-bit_computing)<!-- German WP states that 32-bit slices exist as well, but does not give a reference. --> [arithmetic logic unit](/source/arithmetic_logic_unit) (ALU) and control lines (including [carry](/source/Carry_(arithmetic)) or [overflow](/source/Arithmetic_overflow) signals that are internal to the processor in non-bitsliced [CPU](/source/central_processing_unit) designs).

For example, two 4-bit ALU chips could be arranged side by side, with control lines between them, to form an 8-bit ALU. Any combination is possible: three 1-bit units could make a 3-bit ALU,<ref name="CMSC_2003"/> or even more units to make an ''n''-bit ALU. Four 4-bit ALU chips could be used to build a 16-bit ALU or eight chips to build a 32-bit word ALU. The designer could add as many slices as required to manipulate longer word lengths.

A [microsequencer](/source/microsequencer) or control ROM would be used to execute logic to provide data and control signals to regulate function of the component ALUs.

Known bit-slice microprocessors:
* 2-bit slice:
** [Intel 3000](/source/Intel_3000) family (1974, now discontinued), e.g. Intel 3002 with Intel 3001, second-sourced by [Signetics](/source/Signetics) and [Intersil](/source/Intersil)<ref name="cpushack"/>
** [Signetics](/source/Signetics) 8X02 family (1977, now discontinued)<ref name="Signetics_1977"/>
* 4-bit slice:
** [National](/source/National_Semiconductor) IMP family, consisting primarily of the IMP-00A/520 RALU (also known as MM5750) and various masked ROM microcode and control chips (CROMs, also known as MM5751)
*** National GPC/P / IMP-4 (1973),<ref name="NatSemi_IMP-4"/> second-sourced by [Rockwell](/source/Rockwell_Semiconductor)
*** National IMP-8, an 8-bit processor based on the IMP chipset, using two RALU chips and one CROM chip
*** National [IMP-16](/source/IMP-16), a 16-bit processor based on the IMP chipset, e.g. four RALU chips with one each IMP16A/521D and IMP16A/522D CROM chips (additional optional CROM chips could provide instruction set additions)
** [AMD](/source/AMD) [Am2900](/source/Am2900) family (1975), e.g. AM2901, AM2901A<!-- TTL -->,<ref name="Klar_1989"/> AM2903<!-- TTL --><ref name="Klar_1989"/>
** [Monolithic Memories](/source/Monolithic_Memories) 5700/6700 family (1974)<ref name="Monolithic_6701"/><ref name="Monolithic_5700"/><ref name="MMI_5701"/><ref name="MMI_6701"/> e.g. MMI 5701 / MMI 6701<!-- 6701D -->, second-sourced by [ITT Semiconductors](/source/ITT_Semiconductors)
** [Texas Instruments SBP0400](/source/Texas_Instruments_SBP0400) (1975) and SBP0401, cascadable up to 16 bits
** Texas Instruments [SN74181](/source/SN74181) (1970)
** Texas Instruments [SN74S281](/source/List_of_7400-series_integrated_circuits) with [SN74S282](/source/List_of_7400-series_integrated_circuits)
** Texas Instruments [SN74S481](/source/List_of_7400-series_integrated_circuits) with [SN74S482](/source/List_of_7400-series_integrated_circuits) (1976)<ref name="SN74S481"/>
** [Fairchild](/source/Fairchild_Semiconductor) 33705<!-- CMOS --><ref name="Klar_1989"/>
** Fairchild 9400 (MACROLOGIC), [4700](/source/Fairchild_4700)
** [Motorola](/source/Motorola) M10800 family (1979),<ref name="MC10800"/> e.g. [MC10800](/source/Motorola_MC10800)<!-- ECL --><ref name="Klar_1989"/>
** [Raytheon](/source/Raytheon) RP-16, a 16-bit processor consisting of seven integrated circuits, using four RALU chips and three CROM chips.
thumb|U830C
* 8-bit slice:
** [Four-Phase Systems AL1](/source/Four-Phase_Systems_AL1) (1969, considered to be part of the first microprocessor used in a commercial product)
** Texas Instruments [SN54AS888 / SN74AS888](/source/Texas_Instruments_SN74AS888)
** Fairchild 100K<!-- ECL --><ref name="Klar_1989"/>
** [ZMD](/source/Zentrum_Mikroelektronik_Dresden) {{ill|U830C|de}}<ref name="Kurth-Groß-Hunger_2021_IS"/><ref name="Oppelt_2016"/><ref name="Salomon_2007_U830C"/> (1978/1981), cascadable up to 32 bit
* 16-bit slice:
** AMD [Am29100](/source/Am29100) family
** [Synopsys](/source/Synopsys) [49C402](/source/49C402)
** [ZFT Robotron](/source/ZFT_Robotron)/[ZFTM Dresden](/source/ZFTM_Dresden) {{ill|U840|de|U830C#Nachfolger U84x}} (1979/1982), unreleased<!-- the name U840 was later used for another processor -->

== Historical necessity ==
Bit slicing, although not called that at the time, was also used in computers before [large-scale integrated circuit](/source/large-scale_integration)s (LSI, the predecessor to today's [VLSI](/source/very-large-scale_integration), or very-large-scale integration circuits).

The first bit-sliced machine was [Whirlwind I](/source/Whirlwind_I),<ref name="Whirlwind_I"/> built in 1946–1951.
Its floor plan had a row of "[relay racks](/source/19-inch_rack)" (or "racks" for short) for each group of closely-related and highly-interconnected circuitry, such as the A row with the CPU registers and arithmetic circuitry.  Within a row, the circuitry a single each bit position within a 16-bit word was in a separate rack, such as racks A0–A15 in the A row.

Within a rack, there were panels holding the circuitry for a given function.  The A row racks had, from top to bottom, panels for the Instruction Register ("Program Register" and A Register, the Program Counter, the B and I/O Registers, the Accumulator (where the arithmetic was done), and the Check Register and Comparison Register.  This allowed each rack A0-A15 to be identical and each corresponding panel in these racks to be identical.

Subsequent first-generation machines built with the bit slice concept included the [Memory Test Computer](/source/Memory_Test_Computer) built at MIT as part of the Whirlwind research in 1952–1953, and the [EDSAC 2](/source/EDSAC_2), built at the [University of Cambridge Mathematical Laboratory](/source/University_of_Cambridge_Mathematical_Laboratory) in 1956–1958.

In second generation (discrete transistor) machines, bit slicing was used to partition circuitry into a row of identical plug-in modules, with each module holding one bit of each of several registers. One example<ref name="PDP-6_modules"/> was the [PDP-6](/source/PDP-6), a 36-bit machine with 18-bit memory addresses, in which 9 modules of type 6203 held the 9-bit shift count and floating point exponent registers, 36 modules of type 6205 held the several 36-bit arithmetic registers, and 18 modules of type 6206 held the several 18-bit memory-address related registers.

Prior to the mid-1970s and late 1980s there was some debate over how much bus width was necessary in a given computer system to make it function.{{citation needed|date=June 2025}} Silicon chip technology and parts were much more expensive than today. Using multiple simpler, and thus less expensive, ALUs was seen as a way to increase computing power in a cost-effective manner. While [32-bit](/source/32-bit) microprocessors were being discussed at the time, few were in production.

The [UNIVAC 1100](/source/UNIVAC_1100) compatible series mainframes (one of the oldest series, originating in 1962) has a [36-bit](/source/36-bit) architecture, and the 1100/60 introduced in 1979 used nine [Motorola MC10800](/source/Motorola_MC10800) 4-bit ALU<ref name="MC10800"/> chips to implement the needed word width while using modern integrated circuits.<ref name="Univac_1100"/>

At the time 16-bit processors were common but expensive, and 8-bit processors, such as the [Z80](/source/Z80), were widely used in the nascent home-computer market.

Combining components to produce bit-slice products allowed engineers and students to create more powerful and complex computers at a more reasonable cost, using off-the-shelf components that could be custom-configured. The complexities of creating a new computer architecture were greatly reduced when the details of the ALU were already specified (and [debug](/source/debug)ged).

The main advantage was that bit slicing made it economically possible in smaller processors to use [bipolar transistors](/source/Bipolar_junction_transistor), which, at that time, switched much faster than [NMOS](/source/NMOS_logic) or [CMOS](/source/CMOS) transistors. This allowed much higher clock rates, where speed was needed{{snd}} for example, for [DSP](/source/Digital_signal_processing) functions or [matrix transformation](/source/matrix_transformation){{snd}} or, as in the [Xerox Alto](/source/Xerox_Alto), the combination of flexibility and speed, before single-chip CPUs were able to deliver that.

== Modern use ==
=== Software use on non-bit-slice hardware ===
In more recent times, the term bit slicing was reused by Matthew Kwan<ref name="Kwan"/> to refer to the technique of using a general-purpose CPU to implement multiple parallel simple [virtual machine](/source/virtual_machine)s using general logic instructions to perform single-instruction multiple-data ([SIMD](/source/SIMD)) operations. This technique is also known as [SIMD within a register](/source/SIMD_within_a_register) (SWAR).

This was initially in reference to [Eli Biham](/source/Eli_Biham)'s 1997 article ''A Fast New DES Implementation in Software'',<ref name="DES"/> which achieved significant gains in performance of [DES](/source/Data_Encryption_Standard) by using this method.

=== Bit-sliced superconducting computers ===
To simplify the circuit structure and reduce the hardware cost of [superconducting digital processors](/source/Superconducting_computing) (proposed to run the [MIPS32 instruction set](/source/MIPS_instruction_set)) a 50&nbsp;GHz [superconducting](/source/superconductivity) "4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated".<ref name="Tang_2016"/>

== See also ==
* [Bit-serial architecture](/source/Bit-serial_architecture)

== References ==
{{Reflist|refs=
<ref name="PDP-6_modules">{{cite web |title=PDP-6 Circuit Instruction Manual |date=1966 |website=bitsavers.trailing-edge.com/ |url=https://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_circuitInstr_May66.pdf|access-date=2025-07-29
}}</ref>
<ref name="Whirlwind_I">{{cite web |title=The Whirlwind Computer at CHM |author-first=Guy  |author-last=Fedorkow |date=2018 |website=computerhistory.org |url=https://computerhistory.org/blog/the-whirlwind-computer-at-chm/ |access-date=2025-07-29
}}</ref><ref name="MC10800">{{cite web |title=The MC10800 |author-first=Dieter |author-last=Mueller |date=2012 |website=6502.org |url=http://www.6502.org/users/dieter/a5/a5_6.htm |access-date=2017-11-05 |url-status=live |archive-url=https://web.archive.org/web/20180718220341/http://www.6502.org/users/dieter/a5/a5_6.htm |archive-date=2018-07-18}}</ref>
<ref name="Univac_1100">{{cite web |title=Computers Sperry Univac 1100/60 System |date=January 1983 |publisher=Datapro Research Corporation |location=Delran, NJ, USA |id=70C-877-12 |url=http://bitsavers.org/pdf/univac/1100/datapro/70C-877-12_8301_UNIVAC_1100_60.pdf |access-date=2021-10-11}}</ref>
<ref name="Kwan">{{cite web |title=Bitslice DES |website=darkside.com.au |url=http://www.darkside.com.au/bitslice/ |access-date=2017-11-05}}</ref>
<ref name="DES">{{cite journal |author-first=Eli |author-last=Biham |date=1997 |title=A Fast New DES Implementation in Software |website=cs.technion.ac.il |url=https://www.cs.technion.ac.il/users/wwwb/cgi-bin/tr-info.cgi?1997/CS/CS0891 |access-date=2017-11-05 |archive-date=2017-11-07  |archive-url=https://web.archive.org/web/20171107002919/http://www.cs.technion.ac.il/users/wwwb/cgi-bin/tr-info.cgi?1997/CS/CS0891 |url-status=dead }}</ref>
<ref name="Monolithic_6701">{{cite web |title=6701 - The CPU Shack Museum |website=cpushack.com |url=http://www.cpushack.com/tag/6701/ |access-date=2017-11-05}}</ref>
<ref name="Monolithic_5700">{{cite web |title=5700/6700 - Monolithic Memories |website=en.wikichip.org |url=https://en.wikichip.org/wiki/monolithic_memories/5700 |access-date=2017-11-05}}</ref>
<ref name="MMI_5701">{{cite web |title=File:MMI 5701-6701 MCU (August, 1974).pdf |website=en.wikichip.org |url=https://en.wikichip.org/wiki/File:MMI_5701-6701_MCU_(August,_1974).pdf |access-date=2017-11-05}}</ref>
<ref name="MMI_6701">{{cite web |title=5701/6701 4-Bit Expandable Bipolar Microcontroller Aug74 |url=http://bitsavers.org/components/mmi/bitslice/6701_4-Bit_Expandable_Bipolar_Microcontroller_Aug74.pdf |access-date=2021-05-24}}</ref>
<ref name="SN74S481">{{cite web |url=http://www.cpushack.com/tag/sn74s481/ |title=SN74S481 |work=The CPU Shack Museum |access-date=2017-11-05}}</ref>
<ref name="Signetics_1977">{{cite web |title=Technology Leadership - Bipolar Microprocessor |publisher=[Signetics](/source/Signetics) |id=S2.95 |url=http://bitsavers.org/components/signetics/_dataBooks/1977_Bipolar_Microprocessor.pdf |access-date=2021-10-11 }}</ref>
<ref name="Benadjila_2013">{{cite journal |title=Implementing Lightweight Block Ciphers on x86 Architectures |author-first1=Ryad |author-last1=Benadjila |author-first2=Jian |author-last2=Guo |author-first3=Victor |author-last3=Lomné |author-first4=Thomas |author-last4=Peyrin |date=2014-03-21 |orig-date=2013-07-15 |journal=Cryptology Archive |id=Report 2013/445 |url=https://eprint.iacr.org/2013/445 |access-date=2019-12-28 |url-status=live |archive-url=https://web.archive.org/web/20170817033913/https://eprint.iacr.org/2013/445 |archive-date=2017-08-17}}</ref>
<ref name="CMSC_2003">{{cite web |title=How to Create a 1-bit ALU |website=www.cs.umd.edu |url=https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/onebitALU.html |url-status=dead |archive-url=https://web.archive.org/web/20170508194613/https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/onebitALU.html |archive-date=2017-05-08 |quote=[…] Here's how you would put three 1-bit ALU to create a 3-bit ALU […]}}</ref>
<ref name="cpushack">{{cite web |title=3002 - The CPU Shack Museum |website=cpushack.com |url=http://www.cpushack.com/tag/3002/ |access-date=2017-11-05}}</ref>
<ref name="NatSemi_IMP-4">{{cite web |title=IMP-4 - National Semiconductor |website=en.wikichip.org |url=https://en.wikichip.org/wiki/national_semiconductor/imp-4 |access-date=2017-11-05}}</ref>
<ref name="Tang_2016">{{cite journal |title=4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors |author-first1=Guang-Ming |author-last1=Tang |author-first2=Kensuke |author-last2=Takata |author-first3=Masamitsu |author-last3=Tanaka |author-first4=Akira |author-last4=Fujimaki |author-first5=Kazuyoshi |author-last5=Takagi |author-first6=Naofumi |author-last6=Takagi |id=1300106 |doi=10.1109/TASC.2015.2507125 |journal=[IEEE Transactions on Applied Superconductivity](/source/IEEE_Transactions_on_Applied_Superconductivity) |volume=26 |issue=1 |article-number=2507125 |date=January 2016 |orig-date=2015-12-09 |bibcode=2016ITAS...2607125T |s2cid=25478156 |quote=[…] 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. […] It consists of 3481 [Josephson junction](/source/Josephson_junction)s with an area of 3.09&nbsp;×&nbsp;1.66&nbsp;mm<sup>2</sup>. It achieved the target frequency of 50&nbsp;GHz and a latency of 524&nbsp;ps for a 32-bit operation, at the designed [DC bias](/source/DC_bias) voltage of 2.5&nbsp;mV […] Another 8-bit parallel ALU has been designed and fabricated with target processing frequency of 30&nbsp;GHz<!-- […] However, no bit-slice ALU has been demonstrated so far.--> […] To achieve comparable performance to CMOS parallel microprocessors operating at 2–3&nbsp;GHz, 4-bit bit-slice processing should be performed with a clock frequency of several tens of gigahertz. Several bit-serial arithmetic circuits have been successfully demonstrated with high-speed clocks of above 50&nbsp;GHz […]}}</ref>
<ref name="Klar_1989">{{cite book |title=Digitale Rechenautomaten – Eine Einführung in die Struktur von Computerhardware |language=de |trans-title=Digital Computers – An Introduction into the structure of computer hardware |chapter=5.2 Der Mikroprozessor, ein Universal-Rechenautomat |author-first=Rainer |author-last=Klar |publisher=[Walter de Gruyter & Co.](/source/Walter_de_Gruyter_%26_Co.) |location=Berlin, Germany |series=Sammlung Göschen |volume=2050 |date=1989 |orig-date=1988-10-01 |isbn=3-11011700-2 |page=198 |edition=4th reworked}} (320 pages)</ref>
<ref name="Kurth-Groß-Hunger_2021_IS">{{cite web |title=Integrierte Schaltkreise |language=de |trans-title=Integrated Circuits |editor-first1=Rüdiger |editor-last1=Kurth |editor-first2=Martin |editor-last2=Groß |editor-first3=Henry |editor-last3=Hunger |date=2021-09-27 |orig-date=2006 |website=robotrontechnik.de |url=https://www.robotrontechnik.de/html/komponenten/ic.htm |access-date=2021-12-07 |url-status=live |archive-url=https://web.archive.org/web/20211203191729/https://www.robotrontechnik.de/html/komponenten/ic.htm |archive-date=2021-12-03}}</ref>
<ref name="Oppelt_2016">{{cite web |title=Eastern Bloc DEC PDP |author-first=Dirk |author-last=Oppelt |location=Nuremberg, Germany |website=cpu-collection.de |date=2016 |url=http://www.cpu-collection.de/?tn=0&l0=co&l1=Eastern%20Bloc&l2=DEC+PDP |access-date=2021-12-07 |url-status=live |archive-url=https://web.archive.org/web/20160809164852/http://www.cpu-collection.de/?tn=0&l0=co&l1=Eastern%20Bloc&l2=DEC+PDP |archive-date=2016-08-09}}</ref>
<ref name="Salomon_2007_U830C">{{cite web |title=Einsatzgebiete des U830C und Chipsatz |language=de |trans-title=Applications of the U830C and chipset |author-first=Peter |author-last=Salomon |date=2007-06-25 |website=Robotrontechnik-Forum |url=http://www.robotrontechnik.de/html/forum/thwb/showtopic.php?threadid=2119 |access-date=2021-12-07 |url-status=live |archive-url=https://web.archive.org/web/20191110160714/http://www.robotrontechnik.de/html/forum/thwb/showtopic.php?threadid=2119 |archive-date=2019-11-10}}</ref>
}}

==Further reading==
* {{cite book |last1=Mick |first1=John |last2=Brick |first2=James |date=1980 |title=Bit-Slice Microprocessor Design |url=https://bitsavers.org/components/amd/bitslice/Mick_Bit-Slice_Microprocessor_Design_1980.pdf |location= |publisher=McGraw-Hill |page= |isbn=0-07-041781-4 }}

== External links ==
* {{cite web |title=Untwisted: Bit-sliced TEA time |url=http://plaintext.crypto.lo.gy/article/378/untwisted-bit-sliced-tea-time |url-status=dead |archive-url=https://web.archive.org/web/20131021214351/http://plaintext.crypto.lo.gy/article/378/untwisted-bit-sliced-tea-time |archive-date=2013-10-21}}{{snd}} a bitslicing primer presenting a pedagogical bitsliced implementation of the [Tiny Encryption Algorithm](/source/Tiny_Encryption_Algorithm) (TEA), a [block cipher](/source/block_cipher)

{{Authority control}}

Category:Digital electronics
Category:Central processing unit
Category:University of Cambridge Computer Laboratory
Category:Bit-slice chips

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Adapted from the Wikipedia article [Bit slicing](https://en.wikipedia.org/wiki/Bit_slicing) by Wikipedia contributors ([contributor history](https://en.wikipedia.org/wiki/Bit_slicing?action=history)). Available under [Creative Commons Attribution-ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/). Changes may have been made.