# ARM big.LITTLE

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**ARM big.LITTLE** is a [heterogeneous computing](/source/Heterogeneous_computing) [architecture](/source/Computer_architecture) developed by [Arm Holdings](/source/Arm_Holdings), coupling relatively battery-saving and slower processor cores (*LITTLE*) with relatively more powerful and power-hungry ones (*big*). The intention is to create a [multi-core processor](/source/Multi-core_processor) that can adjust better to dynamic computing needs and use less power than [clock scaling](/source/Clock_scaling) alone. ARM's marketing material promises up to a 75% savings in power usage for some activities.[1] Most commonly, ARM big.LITTLE architectures are used to create a [multi-processor system-on-chip](/source/Multi-processor_system-on-chip) (MPSoC).

In October 2011, big.LITTLE was announced along with the [Cortex-A7](/source/ARM_Cortex-A7_MPCore), which was designed to be [architecturally](/source/Instruction_set_architecture) compatible with the [Cortex-A15](/source/ARM_Cortex-A15_MPCore).[2] In October 2012, ARM announced the [Cortex-A53](/source/ARM_Cortex-A53) and [Cortex-A57](/source/ARM_Cortex-A57) ([ARMv8-A](/source/ARMv8)) cores, which are also intercompatible to allow their use in a big.LITTLE chip.[3] ARM later announced the [Cortex-A12](/source/ARM_Cortex-A12) at [Computex 2013](/source/Computex_Taipei) followed by the [Cortex-A17](/source/ARM_Cortex-A17) in February 2014. Both the Cortex-A12 and the Cortex-A17 can also be paired in a big.LITTLE configuration with the Cortex-A7.[4][5]

## Advantages

For a given library of [CMOS](/source/CMOS) logic, active power increases as the logic switches more per second, while leakage increases with the number of transistors. When a very fast [out-of-order](/source/Out-of-order_execution) CPU is idling at very low speeds, a CPU with much less [leakage](/source/Leakage_(electronics)#In_semiconductors) (fewer transistors) could do the same work. For example, it might use a smaller [memory cache](/source/Cache_(computing)), or a simpler microarchitecture such as removing [out-of-order execution](/source/Out-of-order_execution). big.LITTLE is a way to optimize for both power efficiency and speed in the same system.

## Disadvantages

In practice, a big.LITTLE system can be surprisingly inflexible. One issue is the number and types of power and clock domains that the SoC provides, which may not match the standard power management features offered by an operating system. Another is that the CPUs no longer have equivalent abilities, and matching the right software task to the right CPU becomes more difficult. Most of these problems are being solved by making the electronics and software more flexible.

## Run-state migration

There are three ways[6] for the different processor cores to be arranged in a big.LITTLE design, depending on the actual SoC layout and the [scheduler](/source/Scheduler_(computing)) implemented in the [kernel](/source/Kernel_(operating_system)).[7]

### Clustered switching

The clustered model approach is the first and simplest implementation, arranging the processor into identically sized clusters of "big" or "LITTLE" cores. The operating system scheduler can only see one cluster at a time; when the [load](/source/Load_(computing)) on the whole processor changes between low and high, the system transitions to the other cluster. All relevant data are then passed through the common [L2 cache](/source/L2_cache), the active core cluster is powered off and the other one is activated. A Cache Coherent Interconnect (CCI) is used. This model has been implemented in the [Samsung](/source/Samsung) [Exynos](/source/Exynos) 5 Octa (5410).[8]

### In-kernel switcher (CPU migration)

CPU migration via the in-kernel switcher (IKS) involves pairing up a "big" core with a "LITTLE" core, with possibly [many](/source/Manycore_processor) identical pairs in one chip. Each pair operates as one so-termed *virtual core*, and only one real core is (fully) powered up and running at a time. The "big" core is used when the demand is high and the "LITTLE" core is employed when demand is low. When demand on the virtual core changes (between high and low), the incoming core is powered up, [running state is transferred](/source/Context_switch), the outgoing is shut down, and processing continues on the new core. Switching is done via the [cpufreq](/source/CPU_frequency_scaling) framework. A complete big.LITTLE IKS implementation was added in Linux 3.11. big.LITTLE IKS is an improvement of cluster migration ([§ Clustered switching](#Clustered_switching)), the main difference being that each pair is visible to the scheduler.

A more complex arrangement involves a non-symmetric grouping of "big" and "LITTLE" cores. A single chip could have one or two "big" cores and many more "LITTLE" cores, or vice versa. Nvidia created something similar to this with the low-power "companion core" in their [Tegra 3](/source/Tegra#Tegra_3) [System-on-Chip](/source/System_on_a_chip).

### Heterogeneous multi-processing (global task scheduling)

The most powerful use model of big.LITTLE architecture is [heterogeneous](/source/Heterogeneous_computing) [multi-processing](/source/Multiprocessing) (HMP), which enables the use of all physical cores at the same time. [Threads](/source/Thread_(computing)) with [high priority](/source/Scheduling_(computing)#Priority_scheduling) or computational intensity can in this case be allocated to the "big" cores while threads with less priority or less computational intensity, such as background tasks, can be performed by the "LITTLE" cores.[9] This model also does not require matching numbers of the "big" and "LITTLE" cores.

This model has been implemented in the [Samsung](/source/Samsung) [Exynos](/source/Exynos) starting with the Exynos 5 Octa series (5420, 5422, 5430),[10][11] and [Apple A series](/source/Apple_A_series) processors starting with the [Apple A11](/source/Apple_A11).[12] Another example is the hexa-core [Rockchip RK3399](/source/Rockchip#RK33xx_series) SoC.

## Scheduling

The paired arrangement allows for switching to be done transparently to the [operating system](/source/Operating_system) using the existing [dynamic voltage](/source/Dynamic_voltage_scaling) and [frequency scaling](/source/Dynamic_frequency_scaling) (DVFS) facility. The existing DVFS support in the kernel (e.g. cpufreq in Linux) will simply see a list of frequencies/voltages and will switch between them as it sees fit, just like it does on the existing hardware. However, the low-end slots will activate the 'Little' core and the high-end slots will activate the 'Big' core. This is the early solution provided by Linux's "deadline" CPU scheduler (not to be confused with the I/O scheduler with the same name) since 2012.[13]

Alternatively, all the cores may be exposed to the [kernel scheduler](/source/Scheduler_(computing)), which will decide where each process/thread is executed. This will be required for the non-paired arrangement but could possibly also be used on the paired cores. It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a [SMP](/source/Symmetric_multiprocessing) system are homogenous rather than heterogeneous. A 2019 addition to Linux 5.0 called *Energy Aware Scheduling* is an example of a scheduler that considers cores differently.[14][15]

## Advantages of global task scheduling

- Finer-grained control of workloads that are migrated between cores. Because the scheduler is directly migrating tasks between cores, kernel [overhead](/source/Overhead_(computing)) is reduced and [power](/source/Electric_energy_consumption) savings can be correspondingly increased.
- Implementation in the scheduler also makes switching decisions faster than in the cpufreq framework implemented in IKS.
- The ability to easily support non-symmetrical clusters (e.g. with 2 Cortex-A15 cores and 4 Cortex-A7 cores).
- The ability to use all cores simultaneously to provide improved peak performance throughput of the SoC compared to IKS.

## Successor

In May 2017, ARM announced DynamIQ as the successor to big.LITTLE.[16] DynamIQ is expected to allow for more flexibility and scalability when designing multi-core processors. In contrast to big.LITTLE, it increases the maximum number of cores in a cluster to 8 for Armv8.2 CPUs, 12 for Armv9 and 14 for Armv9.2[17] and allows for varying core designs within a single cluster, and up to 32 total clusters. The technology also offers more fine grained per core voltage control and faster L2 cache speeds.

However, DynamIQ is incompatible with previous ARM designs and is initially only supported by the [Cortex-A75](/source/ARM_Cortex-A75) and [Cortex-A55](/source/ARM_Cortex-A55) CPU cores and their successors.

## References

1. ["big.LITTLE technology"](https://web.archive.org/web/20121022055646/http://www.arm.com/products/processors/technologies/bigLITTLEprocessing.php). ARM.com. Archived from [the original](http://www.arm.com/products/processors/technologies/biglittleprocessing.php) on 22 October 2012. Retrieved 17 October 2012.

1. ["ARM Unveils its Most Energy Efficient Application Processor Ever; Redefines Traditional Power And Performance Relationship With big.LITTLE Processing"](http://www.arm.com/about/newsroom/arm-unveils-its-most-energy-efficient-application-processor-ever-with-biglittle-processing.php). [ARM Holdings](/source/ARM_Holdings). 19 October 2011. Retrieved 2012-10-31.

1. ["ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors"](http://www.arm.com/about/newsroom/arm-launches-cortex-a50-series-the-worlds-most-energy-efficient-64-bit-processors.php). [ARM Holdings](/source/ARM_Holdings). Retrieved 2012-10-31.

1. ["ARM's new Cortex-A12 is ready to power 2014's $200 midrange smartphones"](https://www.theverge.com/2013/6/2/4390076/arm-cortex-a12-mali-t622-v500). *The Verge*. April 2014.

1. ["ARM Cortex A17: An Evolved Cortex A12 for the Mainstream in 2015"](https://archive.today/20140401222906/http://www.anandtech.com/show/7739/arm-cortex-a17). AnandTech. April 2014. Archived from [the original](http://www.anandtech.com/show/7739/arm-cortex-a17) on 1 April 2014.

1. Brian Jeff (18 June 2013). ["Ten Things to Know About big.LITTLE"](https://web.archive.org/web/20130910163539/http://blogs.arm.com/soc-design/1009-ten-things-to-know-about-biglittle/). [ARM Holdings](/source/ARM_Holdings). Archived from [the original](http://blogs.arm.com/soc-design/1009-ten-things-to-know-about-biglittle/) on 10 September 2013. Retrieved 2013-09-17.

1. George Grey (10 July 2013). ["big.LITTLE Software Update"](https://web.archive.org/web/20131004230806/http://www.linaro.org/linaro-blog/2013/07/10/big-little-software-update/). [Linaro](/source/Linaro). Archived from [the original](http://www.linaro.org/linaro-blog/2013/07/10/big-little-software-update/) on 4 October 2013. Retrieved 2013-09-17.

1. Peter Clarke (6 August 2013). ["Benchmarking ARM's big-little architecture"](http://www.embedded.com/electronics-news/4419448/Benchmarking-ARM-s-big-little-architecture). Retrieved 2013-09-17.

1. ["Big.LITTLE Processing with ARM Cortex-A15 & Cortex-A7"](https://web.archive.org/web/20120417183714/http://www.arm.com/files/downloads/big.LITTLE_Final.pdf), [ARM Holdings](/source/ARM_Holdings), September 2013, archived from [the original](http://www.arm.com/files/downloads/big.LITTLE_Final.pdf) on 17 April 2012, retrieved 2013-09-17

1. Brian Klug (2013-09-11). ["Samsung Announces big.LITTLE MP Support in Exynos 5420"](https://web.archive.org/web/20130912085325/http://www.anandtech.com/show/7313/samsung-announces-biglittle-mp-support-in-exynos-5420). [AnandTech](/source/AnandTech). Archived from [the original](http://www.anandtech.com/show/7313/samsung-announces-biglittle-mp-support-in-exynos-5420) on 12 September 2013. Retrieved 2013-09-16.

1. ["Samsung Unveils New Products from its System LSI Business at Mobile World Congress"](https://web.archive.org/web/20140316044700/http://global.samsungtomorrow.com/?p=34630). Samsung Tomorrow. Archived from [the original](http://global.samsungtomorrow.com/?p=34630) on 16 March 2014. Retrieved 26 February 2013.

1. ["The future is here: iPhone X"](https://www.apple.com/newsroom/2017/09/the-future-is-here-iphone-x/). *Apple Newsroom*. Retrieved 2018-02-25.

1. McKenney, Paul (12 June 2012). ["A big.LITTLE scheduler update"](https://lwn.net/Articles/501501/). *LWN.net*

1. Perret, Quentin (25 February 2019). ["Energy Aware Scheduling merged in Linux 5.0"](https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/energy-aware-scheduling-in-linux). *community.arm.com*

1. ["Energy Aware Scheduling"](https://www.kernel.org/doc/html/latest/scheduler/sched-energy.html). *The Linux Kernel documentation*

1. Humrick, Matt (29 May 2017). ["Exploring Dynamiq and ARM's New CPUs"](https://web.archive.org/web/20170529045213/http://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55). Anandtech. Archived from [the original](http://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55) on 29 May 2017. Retrieved 10 July 2017.

1. Ltd, Arm. ["DynamIQ – Arm®"](https://www.arm.com/technologies/dynamiq). *Arm | The Architecture for the Digital World*. Retrieved 2023-10-18.

## Further reading

- David Zinman (25 January 2013). ["big.LITTLE MP status Jan 25, 2013"](https://lwn.net/Articles/534646/). [LWN.net](/source/LWN.net). Retrieved 2013-01-25.
- Nicolas Pitre (15 February 2012). ["Linux support for ARM big.LITTLE"](https://lwn.net/Articles/481055/). [LWN.net](/source/LWN.net). Retrieved 2012-10-18.
- Paul McKenney (12 June 2012). ["A big.LITTLE scheduler update"](https://lwn.net/Articles/501501/). [LWN.net](/source/LWN.net). Retrieved 2012-10-18.
- Jake Edge (5 September 2012). ["KS2012: ARM: A big.LITTLE update"](https://lwn.net/Articles/514063/). [LWN.net](/source/LWN.net). Retrieved 2012-10-18.
- Jon Stokes (20 October 2011). ["ARM's new Cortex A7 is tailor-made for Android superphones"](https://arstechnica.com/gadgets/2011/10/arms-new-cortex-a7-is-tailor-made-for-android-superphones/). [Ars Technica](/source/Ars_Technica). Retrieved 2012-10-31.
- Andrew Cunningham (30 October 2012). ["ARM goes 64-bit with new Cortex-A53 and Cortex-A57 designs"](https://arstechnica.com/information-technology/2012/10/arm-goes-64-bit-with-new-cortex-a53-and-cortex-a57-designs/). [Ars Technica](/source/Ars_Technica). Retrieved 2012-10-31.

## External links

- [big.LITTLE Processing](https://web.archive.org/web/20121022055646/http://www.arm.com/products/processors/technologies/bigLITTLEprocessing.php)
- [big.LITTLE Processing with ARM CortexTM-A15 & Cortex-A7](https://web.archive.org/web/20131017064722/http://www.arm.com/files/downloads/big_LITTLE_Final_Final.pdf) (PDF) (full technical explanation)

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